An Ultralow On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process

IEEE Transactions on Electron Devices

Volumn 34, Issue 4, 1987, Pages 926-930

  Ueda, Daisuke ^a   Takagi, Hiromitsu ^a   Kano, Gota ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS, FIELD EFFECT - FABRICATION;

POWER MOSFET FABRICATION; SELF-ALIGNED PROCESS;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0023330527     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1987.23017     Document Type: Article

References (8)

1. F. Fong, D. Pitzer, and R. J. Zeman, “Power DMOS for high frequency and switching applications,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 322-330, Feb. 1980.
2. I. Yoshida et al., “Thermal stability and secondary breakdown in planar power MOSFET's,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 395-398, Feb. 1980.
3. S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, Feb. 1980.
4. D. Ueda, H. Takagi, and G. Kano, “A new vertical power MOSFET structure with extremely reduced on-resistance,” IEEE Trans. Electron Devices, vol. ED-32, no. 1, Jan. 1985.
5. D. Ueda, H. Takagi, A. Shimano, and G. Kano, “A new vertical sidewall channel power MOSFET with rectangular grooves,” in Extended Abstracts 16th Int. Conf. Solid-State Devices and Materials, pp. 313-316,1984.
6. C. J. Mogab and H. J. Levinstein, “Anisotropic plasma etching of polysilicon,” J. Vac. Sci. Technol., vol. 17, no. 3, pp. 721-730, 1980.
7. R. P. Love, P. V. Gray, and M. S. Adler, “A large area power MOSFET designed for low conduction losses,” IEEE Trans. Electron Devices, vol. ED-31, no. 6, pp. 817-820, June 1984.
8. G. Foder and S. Clemente, “Low voltage FET's slash on-resistance to boost power density,” Electron Design, vol. 32, no. 14, pp. 125-130, July 1984.