Design of PLL-Based Clock Generation Circuits

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 2, 1987, Pages 255-261

  Jeong, Deog Kyoon ^a   Borriellc, Gaetano ^a   Hodges, David A ^a   Katz, Randy H ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE LOCKED LOOPS - CALIBRATION;

CLOCK GENERATION CIRCUITRY; SELF-CALIBRATING TAPPED DELAY LINE; TIMING RELATIONS;

ELECTRONIC CIRCUITS, TIMING;

EID: 0023326940     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052710     Document Type: Article

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