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Volumn 6, Issue 2, 1987, Pages 222-231

On the Repair of Redundant RAM's

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER SIMULATION; INTEGRATED CIRCUITS, VLSI - MANUFACTURE;

EID: 0023314554     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270266     Document Type: Article
Times cited : (84)

References (16)
  • 1
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    • The one-month chip
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    • F. Guteral et al., “The one-month chip,” IEEE Spectrum, vol. 21, no. 9, pp. 40–46, Sept. 1984.
    • (1984) IEEE Spectrum , vol.21 , Issue.9 , pp. 40-46
    • Guteral, F.1
  • 2
    • 0018021595 scopus 로고
    • Multiple word/bit line redundancy for semiconductor memories
    • S. E. Schuster, “Multiple word/bit line redundancy for semiconductor memories,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 698–703, 1978.
    • (1978) IEEE J. Solid-State Circuits , vol.SC-13 , pp. 698-703
    • Schuster, S.E.1
  • 4
    • 0021501354 scopus 로고
    • VLSI testing
    • Oct.
    • T. W. William, “VLSI testing,” Computer, vol. 17, no. 10, pp. 126–136, Oct. 1984.
    • (1984) Computer , vol.17 , Issue.10 , pp. 126-136
    • William, T.W.1
  • 5
    • 0018480756 scopus 로고
    • A fault-tolerant 64k dynamic RAM
    • June
    • R. P. Denker et al., “A fault-tolerant 64k dynamic RAM,” IEEE Trans. Electron Devices, vol. ED-26, June 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26
    • Denker, R.P.1
  • 6
    • 0019016870 scopus 로고
    • Circuit implementation of fusible redundant addresses of RAMs for productivity enhancement
    • B. F. Fitzgerald and E. P. Thoma, “Circuit implementation of fusible redundant addresses of RAMs for productivity enhancement,” IBM J. Res. Develop., vol. 24, pp. 291–298, 1980.
    • (1980) IBM J. Res. Develop. , vol.24 , pp. 291-298
    • Fitzgerald, B.F.1    Thoma, E.P.2
  • 8
    • 0021200061 scopus 로고
    • Defect analysis system speeds test and repair of redundant memories
    • Jan. 12
    • M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories,” Electronics, pp. 175–179, Jan. 12, 1984.
    • (1984) Electronics , pp. 175-179
    • Tarr, M.1    Boudreau, D.2    Murphy, R.3
  • 9
    • 84944980805 scopus 로고
    • A fault-driven comprehensive redundancy algorithm for repair of dynamic RAMs
    • June; also in Proc. 1984 Int. Test Conf., pp. 287–293.
    • J. R. Day, “A fault-driven comprehensive redundancy algorithm for repair of dynamic RAMs,” IEEE Design & Test of Computers, vol. 2, no. 3, pp. 35–44, June 1985; also in Proc. 1984 Int. Test Conf., pp. 287–293.
    • (1985) IEEE Design & Test of Computers , vol.2 , Issue.3 , pp. 35-44
    • Day, J.R.1
  • 10
    • 0019680476 scopus 로고
    • Testing repairable RAMs and mostly good memories
    • R. C. Evans, “Testing repairable RAMs and mostly good memories,” in Proc. Int. Test Conf., 1981, pp. 49–55.
    • (1981) Proc. Int. Test Conf. , pp. 49-55
    • Evans, R.C.1
  • 12
    • 0019013812 scopus 로고
    • Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product
    • C. H. Stapper, A. N. McLaren, and M. Dreckmann, “Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Develop., vol. 24, pp. 398–409, 1980.
    • (1980) IBM J. Res. Develop. , vol.24 , pp. 398-409
    • Stapper, C.H.1    McLaren, A.N.2    Dreckmann, M.3
  • 13
    • 0016072017 scopus 로고
    • Applying a composite model to the IC yield problem
    • R. M. Warner Jr., “Applying a composite model to the IC yield problem,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 86–95, 1974.
    • (1974) IEEE J. Solid-State Circuits , vol.SC-9 , pp. 86-95
    • Warner, R.M.1
  • 14
    • 0016648432 scopus 로고
    • On a composite model to the IC yield problem
    • C. H. Stapper, “On a composite model to the IC yield problem,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 537–539, 1975.
    • (1975) IEEE J. Solid-State Circuits , vol.SC-10 , pp. 537-539
    • Stapper, C.H.1
  • 16
    • 0019061447 scopus 로고
    • 16-k static RAM takes new route to high speed
    • Sept.
    • R. Sud and K. C. Hardee, “16-k static RAM takes new route to high speed,” Electronics, pp. 117–123, Sept. 1980.
    • (1980) Electronics , pp. 117-123
    • Sud, R.1    Hardee, K.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.