Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 1, 1987, Pages 20-27

  Kameyama, Michitaka ^a   Hanyu, Takahiro ^a   Higuchi, Tatsuo ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING; PATTERN RECOGNITION;

PIPELINED IMAGE PROCESSING; QUATERNARY NMOS IC'S;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0023293386     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052666     Document Type: Article

References (15)

1. G. Epstein, G. Frieder, and D. C. Rine, “The development of multiple-valued logic as related to computer science,” Computer, vol. 7, pp. 20–32, Sept. 1974.
2. Z. G. Vranesic and K. C. Smith, Engineering aspects of multiple-valued logic systems,” Computer, vol. 7, pp. 34–41, Sept. 1974.
3. K. C. Smith, “The prospects for multivalued logic: A technology and applications view,” IEEE Trans. Comput., vol. C-30, pp. 619–634, Sept. 1981.
4. T. T. Dao, E. J. McClusky, and L. K. Russell, “Multivalued integrated injection logic,” IEEE Trans. Comput., vol. C-26, pp. 1233–1241, Dec. 1977.
5. K. W. Current, “High density integrated computing circuitry with multiple valued logic,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 127–131, Feb. 1980.
6. M. Stark, “Two bits per cell ROM,” in Proc. COM PON, Feb. 1981, pp. 209–216.
7. M. Brilman, D. Etiemble, J. L. Oursel, and P. Tatareau, “A 4-valued ECL encoder and decoder circuit,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 547–552, June 1982.
8. D. A. Rich, K. C. Naiff, and K. G. Smalley, “A four-state ROM using multilevel process technology,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 174–179, Apr. 1984.
9. K. Preston, Jr. et al., “Basis of cellular logic with some applications in medical image processing,” Proc. IEEE, vol. 67, pp. 826–856, May 1979.
10. G. J. Agin, “Computer vision systems for industrial inspection and assembly,” Computer, vol. 13, pp. 11–20, May 1980.
11. M. Kameyama, K. Suzuki, and T. Higuchi, “Image processing algorithms for a multiple-valued array processor,” in Proc. 13th Int. Symp. MVL, May 1983, pp. 236–241.
12. M. Kameyama and T. Higuchi, “A new architecture of a pipelined image processor based on quaternary logic circuits,” in Proc. 14th Int. Symp. MVL, May 1984, pp. 92–97.
13. C. A. Mead and L. A. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
14. M. Kameyama et al., “An NMOS pipelined image processor using quaternary logic,” in Dig. IEEE Int. Solid-State Circuits Conf., 1985, WPM 8.2, pp. 86–87.
15. A. B. Wittkower, P. H. Rose, and G. Ryding, “Advances in ion implantation production equipment,” Solid-State Technol., vol. 18, no. 12, p. 41, Dec. 1975.