18K 1 mu M CMOS GATE ARRAY WITH HIGH TESTABILITY STRUCTURE.

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1987, Pages 52-55

  Kawashima, Masatoshi ^a   Takechi, Makoto ^a   Ikuzaki, Kunihiko ^a   Kishida, Kuniaki ^a   Itoh, Kazuo ^a   Fujita, Minoru ^a   Nakao, Toshiyuki ^a   Masuda, Ikuro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS - TESTING; TRANSISTORS;

AUTOMATIC TEST PATTERN GENERATION; COMPLEMENTARY MOS (CMOS) GATE ARRAY; HIGH TESTABILITY STRUCTURE;

LOGIC DEVICES;

EID: 0023244207     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)