DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION.

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 1987, Pages 80-86

  Kuninobu, Shigeo ^a   Nishiyama, Tamotsu ^a   Edamatsu, Hisakazu ^a   Taniguchi, Takashi ^a   Takagi, Naofumi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, LSI; LOGIC DESIGN; MATHEMATICAL TECHNIQUES - ALGORITHMS; SEMICONDUCTOR DEVICES, MOS;

MOS MULTIPLIER; REDUNDANT BINARY REPRESENTATION;

COMPUTERS;

EID: 0023170517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/arith.1987.6158706     Document Type: Conference Paper

References (8)