Bipolar Trends

Proceedings of the IEEE

Volumn 74, Issue 12, 1986, Pages 1669-1677

  Ning, Tak H ^a   Tang, Denny D ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIBLIOGRAPHIES; SUBMICROMETER BIPOLAR TECHNOLOGY;

SEMICONDUCTOR DEVICES, BIPOLAR;

INTEGRATED CIRCUITS;

EID: 0022919395     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/PROC.1986.13684     Document Type: Article

References (60)

1. E. J. Rymasewski, J. L. Walsh, and G. W. Wheeler, “Semicon-ductor logic technology in IBM,” IBM I. Res. Develop., vol. 25, 603–616, 1981.
2. S. Brenner, T. A. Bartush, D. J. Swietek, D. C. Banker, F. J. Crispi, D. J. Delotto, D. L. Merrill, J. P. Norsworthy, M. N. Shen, and C. D. Waggoner, “A 10,000 gate bipolar VLSI masterslice utilizing four levels of metal,” in ISSCC Dig. Tech. Papers, pp. 152–153, 1983.
3. E. Gonauser, B. Unger, R. Rauschert, A. Glasl, and K. Schon, “A bipolar 230 ps masterslice cell array with 2600 gates,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 299–305, 1984.
4. M. Usami, S. Hososaka, A. Anzai, K. Otsuka, A. Masaki, S. Murata, M. Ura, and M. Nakagawa, “Status and prospect for bipolar ECL gate array,” in ICCD Dig. Tech. Papers, pp. 272–275, 275, 1983.
5. S. C. Lee and A. S. Bass, “A 2500-gate macro cell array with 250 ps gate delay,” in ISSCC Dig. Tech. Papers, pp. 178–179, 1982. M. Tatsaki, S. Kato, M. Okabe, H. Yakushiji, M. Teri, and T. Noda,” A 280 ps/gate ECL 5000-gate gate array,” in Proc. IEEE Custom Integrated Circuit Conf., pp. 18–21, 1985.
6. W. R. Heller, C. G. Hsi, and W. F. Mikhail, “Wireability-de-signing signing wiring space for chips and chip packages,” IEEE Des. Test, vol. 1, pp. 43–51, 1984.
7. W. Klein, E. F. Miersch, R. Remshardt, H. Schettler, U. Schultz, and Zuhlke, “A study on bipolar VLSI gate-arrays assuming four layers of metal,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 472–480, 1982.
8. K. °glue, S. Ohwaki, and Y. Katoo, “16 K-bit high speed bi-polar static RAM,” Hitachi Rev., vol. 33, no. 2, pp. 77–80, 1984. Y. Okaj i ma, K. Toyoda, T. Awaya, K. Tanaka, and Y. Nakamu ra, “64 Kb ECL RAM with redundancy,” in ISSCC Dig. Tech. Papers, pp. 48–49, 1985.
9. W. E. Harding, “Semiconductor manufacturing in IBM, 1957 to the present: A perspective,” IBM J. Res. Develop., vol. 25, pp. 647–658, 1981.
10. S. K. Wiedmann, “Advancements in bipolar VLSI circuits and technologies,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 282–291, 291, 1984.
11. T. Sakai and M. Suzuki, “Super self-aligned bipolar tech-nology,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 16–19, 1983. S. Konaka, Y. Yamamoto, and T. Sakai, “A 30 ps Si bipolar IC using super self-aligned process technology,” in Extended Abstracts 16th Int. Conf. on Solid-State Devices and Mate-rials, pp. 209–2121, 1984.
12. Y. Tamaki, T. Shiba, N. Honma, S. Mizuo, and A. Hayasaka, “New U-groove isolation technology for high-speed bipolar memory,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 24–25, 1983. H. Yamamoto, 0. Mizuno, T. Kubota, M. Nakamae, H. Shi raki, and Y. lkushima, “High-speed performance of a basic ECL gate with 1.25 micron design rule,” in Symp. VLSI Technol-ogy, Dig. Tech. Papers, pp. 38–39, 1981.
13. T. Nakamuara, K. Nakazato, T. Miyazaki, T. Okabe, and M. Nagata, “Integrated 84 Ps ECL with I2L,” in 155CC Dig. Tech. Papers, pp. 152–153, 1984. T. Nakamura, T. Miyazaki, S. Takahashi, T. Kure, T. Okabe, and M. Nagata, “Self-aligned transistor with sidewall base electrode,” IEEE Trans. Electron Devices, vol. ED-29, pp. 596–600, 600, 1982.
14. D. D. Tang, P. M. Solomon, T. H. Ning, R. D. Isaac, and R. E. Burger, “1.25 Am deep-groove-isolated self-aligned bipolar circuits,” in ISSCC Dig. Tech. Papers, pp. 242–243, 1982; also IEEE J. Solid-State Circuits, vol. SC-17, pp. 925–931, 1982. D. D. Tang, G. P. Li, C. T. Chuang, D. Danner, M. B. Ketchen, J. Mauer, M. Smyth, M. Manny, J. D. Cressler, B. Ginsberg, E. Petrillo, T. H. Ning, C. C. Hu, and H. S. Park, “73 ps bipolar ECL circuits,” in ISSCC Dig. Tech. Papers, 1986.
15. T. Sakai, Y. Yamamoto, K. Kobayashi, Y. Yamauti, T. lshitani, and T. Sudo, “Elevated electrode integrated circuits,” IEEE Trans. Electron Devices, vol. ED-26, pp. 379–385, 1979.
16. K. Okada, K. Aomura, T. Nakamura, and H. Shiba, “A new polysilicon process for a bipolar device—PSA technology,” IEEE Trans. Electron Devices, vol. ED-26, pp. 385–389, 1979. H. Nakashiba, I. Ishida, K. Aomura, and T. Nakamura, “An advanced PSA technology for high-speed bipolar LSI,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 455–459, 1980. T. Tashiro, H. Takemura, T. Kamiya, F. Tokuyoshi, S. Ohl, H. Shiraki, M. Nakamae, and T. Nakamura, “An 80 Ps ECL circuit with high current density transistor,” in IEDM Tech. Dig., pp. 686–689, 1984.
17. T. H. Ning, R. D. Isaac, P. M. Solomon, D. D. Tang, and H. N. Yu, “Self-aligned npn bipolar transistors,” in IEDM Tech. Dig., 823–824, 1980.
18. D. D. Tang, T. H. Ning, S. K. Wiedmann, R. D. Isaac, G. C. Feth, and H. N. Yu, “Subnanosecond self-aligned MTL/121_ Circuits,” in IEDM Tech. 1979.
19. D. D. Tang, V. J. Silvestri, H. N. Yu, and A. Reisman, “A sym-metrical bipolar transistor,” in IEDM Tech. Dig., pp. 58–61, 1980.
20. M. Shimuzu, and H. Kitabayashi, “BEST (base-emitter self-aligned aligned technology), a new fabrication method for bipolar LSI,” in IEDM Tech. 1979.
21. S. Horiguchi, M. Suzuki, H. !chino, S. Konaka, and T. Sakai, An 80 ps 2500-gate bipolar macrocell array,” in ISSCC Dig. Tech. Papers, pp. 198–199, 1985.
22. H. Miyanaga, S. Konaka, Y. Yamamoto, and T. Sakai, “A 0.85 ns 1 Kb bipolar ECL RAM,” in Extended Abstracts 16th Int. Conf. on Solid-State Devices and Materials, pp. 225–228, 1984.
23. M. Suzuki, K. Hagimoto, H. Ichino, and S. Konaka, “A 9-GHz frequency divider using Si bipolar super-self-aligned process technology,” IEEE Trans. Electron Device Lett., vol. EDL-6, pp. 1985.
24. M. Suzuki, K. Matsuhiro, and Y. Kobayashi, “A bipolar 32-bit VLSI processor,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 114–115, 1982.
25. D. D. Tang and R. E. Burger, “Design considerations of dense bipolar PLA’s,” to be published.
26. J. Lohstroh, “Devices and circuits for bipolar (V)LSI,” Proc. IEEE, vol. 69, pp. 265–279, 1981.
27. D. D. Tang and T. H. Ning, “Advances in bipolar IC tech-nology,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 20–23, 1985.
28. P. M. Solomon, “A comparison of semiconductor devices for high-speed logic,” Proc. IEEE, vol. 70, 489–509, 1982.
29. D. D. Tang and P. M. Solomon, “Bipolar transistor design for optimized power-delay log i c circuits,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 679–684, 1979.
30. P. M. Solomon and D. D. Tang, “Bipolar circuit scaling,” in ISSCC Dig. Tech. Papers, pp. 86–87, 1979.
31. T. H. Ning and R. D. Isaac, “Effect of emitter contact on cur-rent gain of silicon bipolar devices,” IEEE Trans. Electron De-vices, vol. ED-27, pp. 2051–2055, 1980.
32. H. L. Stover, “Stepping into the 80's with die-by-die alignment,” Solid-State Technol., vol. 24, pp. 112–120, May, 1981.
33. T. H. Ning and D. D. Tang, “Method for determining the emitter and base series resistances of bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 409–412, 1984.
34. K. Toyada, M. Tanaka, H. Isogai, C. Ono, Y. Kawabe, and H. Coto, “A 15 ns 16 Kb ECL RAM with a pnp load cell,” in ISSCC Dig. Tech. Papers, pp. 108–109, 1983.
35. R. J. Houghton, P. P. Boulay, and R. F. Penoyer, “A 72 Kb bi-polar DRAM,” in ISSCC Dig. Tech. Papers, pp. 70–71, 1982.
36. P. van Halen and D. L. Pulfrey, “High-gain bipolar transistors with polysilicon tunnel junction emitter contacts,” IEEE Trans. Electron Devices, vol. ED-32, 1307–1313, 1985.
37. J. Graul, A. Glasl, and H. Murrmann, “High-performance tran-sistors with arsenic-implanted polysil emitter,” IEEE J. Solid-State State Circuits, vol. SC-11, pp. 491–495, 1976.
38. H. C. de Graaf and J. G. de Groot, “The SIS tunnel emitter: A theory for emitter with thin interface layers,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1771–1776, 1979.
39. B. Soerowirdjo and P. Ashburn, “Effect of surface treatments on the electrical characteristics of bipolar transistors with polysilicon emitters,” Solid-State Electron., vol. 26, pp. 495–498, 498, 1983.
40. F. Barson, R. Kastl, B. Kemlage, and A. Michel, “Shallow bi-polar transistor profiles by diffusion from implanted poly-silicon,” silicon,” in VLSI Science and Technology, 1982, C. J. Dell'Oca and W. M. Bullis, Eds. (The Electrochemical Soc., 1982), pp. 282–289.
41. P. Ashburn and B. Soerowirdjo, “Comparison of experimen-tal and theoretical results on polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 853–859, 1984.
42. A. Neugroschel, M. Arienzo, Y. Komem, and R. D. Isaac, “Ex-perimental study of the minority-carrier transport at the poly-silicon-monosilicon silicon-monosilicon interface,” IEEE Trans. Electron Devices, vol. ED-32, pp. 807–816, 1985.
43. J. M. C. Stork, C. Y. Wong, and M. Arienzo, “Polysilicon emitter resistance and carrier transport studies,” in Symp. VLSI Technology, Tech. 44–45, 1985.
44. M. C. Wilson, N. Jorgensen, G. R. Booker, and P. C. Hunt, “Electrical and microstructural investigation into the effect of arsenic emitter concentration on the enhanced gain polysilicon silicon emitter bipolar transistor,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 46–47, 1985.
45. Z. Yu, B. Ricco, and R. W. Dutton, “A comprehensive ana-lytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, 31, pp. 773–784, 1984.
46. T. H. Ning, D. D. Tang, and P. M. Solomon, “Scaling prop-erties of bipolar devices,” in IEDM Tech. Dig., pp. 61–64, 1980.
47. T. H. Ning, “Possibilities and limitations of bipolar devices,” in Extended Abstracts 16th Int. Conf. on Solid-State Devices and Materials, pp. 205–208, 1984.
48. F. Tokuyoshi, H. Takemura, T. Tashiro, and S. Ohi, “A 2.3 ns access time 4K EC L RAM,” in ISSCC Dig. Tech. Papers, pp. 220–221, 221, 1984.
49. J. M. C. Stork and J. D. Cressler, “Performance degradation due to emitter resistance in polysilicon emitter bipolar tran-sistors,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 47–48, 48, 1986.
50. R. J. Blumberg and S. Brenner, “A 1500-gate random logic LSI masterslice,” in ISSCC Dig. Tech. Papers, 60–61, 1979.
51. K. Hart and A. Slob, “Integrated injection logic: A new approach to LSI,” IEEE). Solid-State Circuits, vol. SC-7, pp. 346–351, 351, 1972.
52. H. H. Berger and S. K. Wiedmann, “Merged-transistor logic (MTL)—A low cost bipolar logic concept,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 340–346, 1972.
53. T. H. Ning, R. D. Isaac, P. M. Solomon, D. D. Tang, H. N. Yu, G. C. Feth, and S. K. Wiedmann, “Self-aligned bipolar tran-sistor for high-performance and low-power-delay VLSI,” IEEE Trans. Electron Devices, vol. ED-28, pp. 1010–1013, 1981.
54. S. K. Wiedmann and D. D. Tang, “High-speed split-emitter MTL/ FL memory cell,” in ISSCC Dig. Tech. Papers, pp. 158–159, 159, 1981. S. K. Wiedmann, D. D. Tang, and R. Beresford, “High-speed split-emitter MTL/ FL memory cell,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 429–434, 1981.
55. S. K. Wiedmann and H. H. Berger, “Bipolar complementary logic (CTL), “ in Proc. 1st European Solid-State Circuit Conf., pp. 36–39, 1975.
56. H. Higuchi, A. Anzai, N. Homma, and A. Hayasaka, “High-per-formance bipolar LSI; their present status and future,” in Symp. VLSI Technology, Dig. Tech. Papers, pp. 110–113, 1982.
57. S. K. Wiedmann, “Charge buffer logic (CBL)—A new com-plementary bipolar circuit concept,” in Symp. VLSI Tech-nology, Dig. Tech. Papers, pp. 38–39, 1985.
58. Y. Kobayashi, Y. Yamamoto, and T. Sakai, “A new bipolar structure for very high-speed VLSI,” in Symp. VLSI Technol-ogy, Tech. 1985.
59. H. Sadamatsu, M. Inoue, A. Matsuzawa, A. Kanda, and H. Shi-moda, “New self-aligned complementary bipolar transistors using selective-oxidation mask,” in IEDM Tech. Dig., pp. 753–756, 756, 1984.
60. G. A. Sai-Halasz and D. D. Tang, “Soft-error rates in bipolar static RAM’s,” in IEDM Tech. Dig., pp. 344–347, 1983.