n-Channel Lateral Insulated Gate Transistors: Part I—Steady-State Characteristics

IEEE Transactions on Electron Devices

Volumn 33, Issue 12, 1986, Pages 1956-1963

  Pattanayak, Deva N ^a   Robinson, A L ^a   Chow, T Paul ^a   Adler, Michael S ^a   Baliga, B Jayant ^a   Wildi, Eric J ^a  

^a GE GLOBAL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED LAYERS; CURRENT HANDLING CAPACITY INCREASE; N-CHANNEL LATERAL INSULATED GATE TRANSISTOR; STEADY-STATE CHARACTERISTICS; SURFACE SHORTS;

TRANSISTORS;

EID: 0022909399     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22853     Document Type: Article

References (12)

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6. Unpublished.
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10. —, “A method for terminating mesh lines in finite difference formulations of the semiconductor device equations,” Solid-State Electron., vol. 23, pp. 845–853, 1980.
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