-
1
-
-
84937350085
-
-
Dec.
-
J. J. Ebers and J. L. Moll, Proc. IRE, vol. 42, no. 12, pp. 1761–1772, 1772, Dec. 1954.
-
(1954)
Proc. IRE
, vol.42
, Issue.12
, pp. 1761-1772
-
-
Ebers, J.J.1
Moll, J.L.2
-
3
-
-
84939736306
-
-
W. L. Engl et al., Proc. IEEE, vol. 71, no. 10, 1983.
-
(1983)
Proc. IEEE
, vol.71
, Issue.10
-
-
Engl, W.L.1
-
6
-
-
84939753727
-
Computer-aided design and optimization for semiconductor device fabrication
-
(ed. by H. F. Huff and E. Sirth)
-
P. L. Shah, “Computer-aided design and optimization for semiconductor device fabrication (ed. by H. F. Huff and E. Sirth), Semiconductor Silicon, 1977.
-
(1977)
Semiconductor Silicon,.
-
-
Shah, P.L.1
-
7
-
-
0003760989
-
SUPREM I-A program for IC process modeling and simulation
-
May 77–006
-
D. A. Antoniadis, S. E. Hansen, R. W. Dutton, and A. G. Gon-zalez, “SUPREM I-A program for IC process modeling and simulation,” Stanford Electronics Lab., Stanford University, Tech. Rep., SEL 77–006, May 1977.
-
(1977)
Stanford Electronics Lab., Stanford University, Tech. Rep., SEL
-
-
Antoniadis, D.A.1
Hansen, S.E.2
Dutton, R.W.3
Gon-zalez, A.G.4
-
9
-
-
0003760989
-
SUPREM II-A program for IC process modeling and simulation
-
June
-
D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREM II-A program for IC process modeling and simulation,” Stan-ford Electronics Lab., Stanford University, Tech. Rep. SEL 78–020, 020, June 1978.
-
(1978)
Stan-ford Electronics Lab., Stanford University, Tech. Rep. SEL 78–020
-
-
Antoniadis, D.A.1
Hansen, S.E.2
Dutton, R.W.3
-
10
-
-
0020845356
-
VLSI process modeling-SUPREM III
-
Nov.
-
C. P. Ho, J. D. Plummer, S. E. Hansen, and R. W. Dutton, “VLSI process modeling-SUPREM III,” IEEE Trans. Electron De-vices, vol. ED-30, no. 11, Nov. 1983.
-
(1983)
IEEE Trans. Electron De-vices
, vol.ED-30
, Issue.11
-
-
Ho, C.P.1
Plummer, J.D.2
Hansen, S.E.3
Dutton, R.W.4
-
11
-
-
0020180740
-
-
K. A. Salsburg and H. H. Hansen, IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1004–1011, 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, Issue.9
, pp. 1004-1011
-
-
Salsburg, K.A.1
Hansen, H.H.2
-
14
-
-
1642589946
-
Composite-A complete modeling program of silicon technology
-
Oct.
-
J. Lorenz et al., “Composite-A complete modeling program of silicon technology,” IEEE Trans. Electron Devices, vol. ED-32, 32, no. 10, pp. 1977–1986, Oct. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, Issue.32
, pp. 1977-1986
-
-
Lorenz, J.1
-
15
-
-
0020847614
-
-
B. C. Maldonado et al., IEEE Trans. Electron Devices, vol. ED-30, 30, no. 11, pp. 1462–1469, 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, Issue.30
, pp. 1462-1469
-
-
Maldonado, B.C.1
-
16
-
-
84913822809
-
-
R. Tielert, IEEE J. Solid-State Circuits, vol. SC-15, no. 4, pp. 544–548, 548, 1980.
-
(1980)
IEEE J. Solid-State Circuits
, vol.SC-15
, Issue.4
, pp. 544-548
-
-
Tielert, R.1
-
18
-
-
0016049508
-
-
Apr.
-
P. H. Langer and J. I. Goldstein, J. Electrochem. Soc., vol. 121, no. 4, pp. 563, Apr. 1974.
-
(1974)
J. Electrochem. Soc.
, vol.121
, Issue.4
, pp. 563
-
-
Langer, P.H.1
Goldstein, J.I.2
-
20
-
-
0018457024
-
A general simulator for VLSI lithog-raphy and etching processes: Part I: Applications to projection lithography
-
Apr.W. G. Oldham, et. al., “A general stimulator for VLSI lithog-raphy and etching processes: Part II: Application to depo-sition and etching, ” IEEE Trans. Electron Devices, vol. ED-27, p. 1455, Aug. 1980
-
W. G. Oldham et al., “A general simulator for VLSI lithog-raphy and etching processes: Part I: Applications to projection lithography,” IEEE Trans. Electron Devices, vol. ED-26, p. 717, Apr. 1979. W. G. Oldham, et al., “A general stimulator for VLSI lithog-raphy and etching processes: Part II: Application to depo-sition and etching,” IEEE Trans. Electron Devices, vol. ED-27, p. 1455, Aug. 1980.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, pp. 717
-
-
Oldham, W.G.1
-
21
-
-
0020878226
-
-
S. M. Hu et al., J. App!. Phys., vol. 54, no. 12, pp. 6912–6922, 1983.
-
(1983)
J. Appl. Phys.
, vol.54
, Issue.12
, pp. 6912-6922
-
-
Hu, S.M.1
-
24
-
-
0018331014
-
-
T. C. May and M. H. Woods, IEEE Trans. Electron Devices, vol. ED-26, no. 1, pp. 2–9, 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, Issue.1
, pp. 2-9
-
-
Mayand, T.C.1
Woods, M.H.2
-
25
-
-
0020141359
-
-
R. K. Cook and J. Frey, IEEE Trans. Electron Devices, vol. ED-29, 29, pp. 970–977, 1982.
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
, Issue.29
, pp. 970-977
-
-
Cook, R.K.1
Frey, J.2
-
30
-
-
0001738944
-
Iterative methods in semiconductor de-vice simulation
-
Oct.
-
C. S. Rafferty etal., “Iterative methods in semiconductor de-vice simulation,” IEEE Trans. Electron Devices, vol. ED-32, no. 10, pp. 2018–2077, Oct. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, Issue.10
, pp. 2018-2077
-
-
Rafferty, C.S.1
-
31
-
-
0020135188
-
Monte Carlo particle modeling of small semi-conductor devices
-
C. Moglestue, “Monte Carlo particle modeling of small semi-conductor devices,” Comp. Meth. App!. Mech. Eng., vol. 30, pp. 173–208, 1982.
-
(1982)
Comp. Meth. Appl. Mech. Eng.
, vol.30
, pp. 173-208
-
-
Moglestue, C.1
-
33
-
-
84939765419
-
Optimized and reliable LDD structure for 1 gm NMOSFET based on substrate current analysis
-
Dec. 9–12
-
Y. Matsumoto et at, “Optimized and reliable LDD structure for 1 gm NMOSFET based on substrate current analysis,” in Tech. Dig. IEEE Int. Electron Device Meet., paper 27.7, pp. 621–624 624 (Dec. 9–12, 1984).
-
(1984)
Tech. Dig. IEEE Int. Electron Device Meet., paper 27.7
, pp. 621-624
-
-
Matsumoto, Y.1
-
34
-
-
0019049847
-
Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transis-tor
-
Aug.
-
S. Ogura et al., “Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transis-tor,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1359–1367, 1367, Aug. 1980.
-
(1980)
IEEE Trans. Electron Devices
, vol.ED-27
, Issue.8
, pp. 1359-1367
-
-
Ogura, S.1
-
35
-
-
0022291932
-
Process and device considerations for micron and submicron CMOS technology
-
Dec. 1-4
-
L. C. Parrillo, “Process and device considerations for micron and submicron CMOS technology,” in Tech. Dig. IEEE Int. Electron Device Meet., paper 15.1, pp. 398–402 (Dec. 1-4,1985).
-
(1985)
Tech. Dig. IEEE Int. Electron Device Meet., paper 15.1
, pp. 398-402
-
-
Parrillo, L.C.1
-
39
-
-
0038185073
-
The physics and modeling of latch-up and CMOS integrated circuits
-
Ph.D. dissertation, Stanford University, Stanford, CA
-
D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Ph.D. dissertation, Stanford University, Stanford, CA, 1980.
-
-
-
Estreich, D.B.1
-
40
-
-
0019683280
-
Design model for bulk CMOS scaling enabling accurate latch-up prediction
-
A. Wieder, C. Werner, and J. Harter, “Design model for bulk CMOS scaling enabling accurate latch-up prediction,” in Tech. Dig. IEEE Int. Electron Device Meet., pp. 34–35, 1981.
-
(1981)
Tech. Dig. IEEE Int. Electron Device Meet.
, pp. 34-35
-
-
Wieder, A.1
Werner, C.2
Harter, J.3
-
41
-
-
0022100877
-
An im-proved circuit model for CMOS latchup
-
July
-
J. E. Hall, J. A. Seitchik, L. A. Arledge, and P. Yang, “An im-proved circuit model for CMOS latchup,” IEEE Electron De-vice Lett., vol. EDL-6, pp. 320–323, July 1985.
-
(1985)
IEEE Electron De-vice Lett.
, vol.EDL-6
, pp. 320-323
-
-
Hall, J.E.1
Seitchik, J.A.2
Arledge, L.A.3
Yang, P.4
-
42
-
-
84939361874
-
Two-dimensional sim-ulation of latchup in CMOS structures
-
June
-
G. J. Hu, M. R. Pinto, and S. Kordic, “Two-dimensional sim-ulation of latchup in CMOS structures,” presented at the De-vice Research Conf., June 1982.
-
(1982)
De-vice Research Conf.
-
-
Hu, G.J.1
Pinto, M.R.2
Kordic, S.3
-
43
-
-
0021640239
-
Characterization and modeling of a latch-up free 1-Am CMOS technology
-
Y. Taur, W. H. Chang, and R. H. Dennard, “Characterization and modeling of a latch-up free 1-Am CMOS technology,” in Tech. Dig. Int. Electron Device Meet., p. 398, 1984.
-
(1984)
Tech. Dig. Int. Electron Device Meet.
, pp. 398
-
-
Taur, Y.1
Chang, W.H.2
Dennard, R.H.3
-
44
-
-
0022012209
-
Accurate trigger condition analysis for CMOS latchup
-
Feb.
-
M. R. Pinto and R. W. Dutton, “Accurate trigger condition analysis for CMOS latchup,” IEEE Electron Device Lett., vol. EDL-6, pp. 100–102, Feb. 1985.
-
(1985)
IEEE Electron Device Lett.
, vol.EDL-6
, pp. 100-102
-
-
Pinto, M.R.1
Dutton, R.W.2
-
45
-
-
84916436169
-
Transient simulation of silicon de-vices and circuits
-
Oct.
-
R. E. Bank, W. M. Coughran, Jr., W. Fichtner, E. H. Grosse, D. J. Rose, and R. K. Smith, “Transient simulation of silicon de-vices and circuits,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1992–2007, Oct. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 1992-2007
-
-
Bank, R.E.1
Coughran, W.M.2
Fichtner, W.3
Grosse, E.H.4
Rose, D.J.5
Smith, R.K.6
-
46
-
-
0041967131
-
Two-dimensional numerical analysis of latchup in a VLSI CMOS technology
-
Oct.
-
E. C. Sangiorgi, M. R. Pinto, S. E. Swirhun, and R. W. Dutton, “Two-dimensional numerical analysis of latchup in a VLSI CMOS technology,” IEEE Trans. Electron Devices, vol. ED-32, pp. 2117–2130, Oct. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 2117-2130
-
-
Sangiorgi, E.C.1
Pinto, M.R.2
Swirhun, S.E.3
Dutton, R.W.4
-
48
-
-
11044224832
-
A critique of the theory of p-n-p-n devices
-
Sept.
-
J. F. Gibbons, “A critique of the theory of p-n-p-n devices,” IRE Trans. Electron Devices, vol. ED-11, pp. 406–413, Sept. 1964.
-
(1964)
IRE Trans. Electron Devices
, vol.ED-11
, pp. 406-413
-
-
Gibbons, J.F.1
-
49
-
-
0003672607
-
PISCES-II: Pois-son and continuity equation solver
-
Stanford Electronics Lab., Stanford Univ., Tech. Rep., Sept.
-
M. R. Pinto, C. S. Rafferty, and R. W. Dutton, “PISCES-II: Pois-son and continuity equation solver,” Stanford Electronics Lab., Stanford Univ., Tech. Rep., Sept. 1985.
-
-
-
Pinto, M.R.1
Rafferty, C.S.2
Dutton, R.W.3
-
50
-
-
0042875279
-
PISCES II-B: Supplementary report
-
Stanford Univ., Tech. Rep., Sept.
-
M. R. Pinto, C. S. Rafferty, H. R. Yeager, and R. W. Dutton, “PISCES II-B: Supplementary report,” Stanford Electronics Lab., Stanford Univ., Tech. Rep., Sept. 1985.
-
(1985)
Stanford Electronics Lab.
-
-
Pinto, M.R.1
Rafferty, C.S.2
Yeager, H.R.3
Dutton, R.W.4
-
51
-
-
0020704130
-
A transient analysis of latchup in bulk CMOS
-
R. R. Troutman, and H. P. Zappe, “A transient analysis of latchup in bulk CMOS,” IEEE Trans. Electron Devices, vol. ED-30, 30, pp. 170–179, 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, Issue.30
, pp. 170-179
-
-
Troutman, R.R.1
Zappe, H.P.2
-
52
-
-
47349120157
-
A statistical approach to the design of diffusion junction transistors
-
D. P. Kennedy et al., “A statistical approach to the design of diffusion junction transistors,” IBM J. Res. Develop., vol. 8, p. 482, 1964.
-
(1964)
IBM J. Res. Develop.
, vol.8
, pp. 482
-
-
Kennedy, D.P.1
-
53
-
-
84942211246
-
Statistical analysis of propagation delay in digital integrated circuits
-
Feb. 16–18
-
P. E. Fox et al., “Statistical analysis of propagation delay in digital integrated circuits,” in Tech. Dig. IEEE Int. Solid State Circuits Conf., paper WPM 6.3, pp. 66–67 (Feb. 16–18, 1972).
-
(1972)
Tech. Dig. IEEE Int. Solid State Circuits Conf., paper WPM 6.3
, pp. 66-67
-
-
Fox, P.E.1
-
54
-
-
0017547756
-
Experimental study of Gummel-Poon model parameter correlations for bipolar junction transis-tors
-
Oct.
-
D. A. Divekar et al., “Experimental study of Gummel-Poon model parameter correlations for bipolar junction transis-tors,” IEEE J. Solid-State Circuit, vol. SC-12, no. 5, pp. 552–559, Oct. 1977.
-
(1977)
IEEE J. Solid-State Circuit
, vol.SC-12
, Issue.5
, pp. 552-559
-
-
Divekar, D.A.1
-
55
-
-
0021202647
-
FABRICS II: A statistically based IC fabri-cation process simulator
-
Jan.
-
S. N. Nasif et al., “FABRICS II: A statistically based IC fabri-cation process simulator,” IEEE Trans. Computer-Aided Des., vol. CAD-3, no. 1, pp. 40–46, Jan. 1984.
-
(1984)
IEEE Trans. Computer-Aided Des.
, vol.CAD-3
, Issue.1
, pp. 40-46
-
-
Nasif, S.N.1
-
56
-
-
84939739549
-
Semi equipment communications standards (SECS I)
-
Mountain View, CA
-
C. Clare, “Semi equipment communications standards (SECS I),” in Book of Semi Standards SEMI, Mountain View, CA, 1985.
-
(1985)
Book of Semi Standards SEMI
-
-
Clare, C.1
-
57
-
-
84976854615
-
FABLE: A programming language solution to IC process automation problems
-
June
-
H. L. Ossher etal. “FABLE: A programming language solution to IC process automation problems,” in Proc. SIGPLAN ‘83, June 1983.
-
(1983)
Proc. SIGPLAN '83
-
-
Ossher, H.L.1
-
58
-
-
0019021929
-
Shallow junctions by high dose as implants in Si: Experiments and modeling
-
M. Y. Tsai etal., “Shallow junctions by high dose as implants in Si: Experiments and modeling,” J. App!. Phys., vol. 51, no. 6, pp. 3230–3235, 1980.
-
(1980)
J. Appl. Phys.
, vol.51
, Issue.6
, pp. 3230-3235
-
-
Tsai, M.Y.1
|