Design Procedures for Differential Cascode Voltage Switch Circuits

IEEE Journal of Solid-State Circuits

Volumn 21, Issue 6, 1986, Pages 1082-1087

  Chu, Kan M ^a   Pulfrey, David L ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, COMPARATOR; ELECTRONIC CIRCUITS, SWITCHING; MATHEMATICAL TECHNIQUES - TREES; SEMICONDUCTOR DEVICES, MOS;

CMOS; DCVS TREES; KARNAUGH MAPPING;

LOGIC CIRCUITS;

EID: 0022867125     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1986.1052651     Document Type: Article

References (7)

1. L. G. Heller and W. R. Griffin, “Cascode voltage switch logic: A differential CMOS logic family,” in ISSCC Dig. Tech. Papers, 1984, pp. 16–17.
2. C. K. Erdelyi, “Random logic design utilizing single-ended cascode voltage switch circuits in NMOS,” IEEE J. Solid-State Circuits, vol. SC-20, 591–594, 1985.
3. R. K. Brayton and C. McMullen, “The decomposition and factorization of Boolean expressions,” in Proc. IEEE Int. Symp. Circuits Syst. (Rome, Italy), 1982, pp. 49–54.
4. S. Muroga, Logic Design and Switching Theory. New York: Wiley, 1979, 163–180.
5. M. D. F. Schlag, E. J. Yoffa, P. S. Hauge, and C. K. Wong, “A method for improving cascode-switch macro wirability,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 150–155, Apr. 1985.
6. K. M. Chu, “ Cascade voltage switch logic,” M.A.Sc. thesis, Univ. of British Columbia, Vancouver, Canada, 1986
7. T. C. Lo, “Regular layout FET carry look-ahead circuit,” IBM Tech. Disclosure Bull., vol. 26, pp. 6202, Apr. 1984.