메뉴 건너뛰기




Volumn C-35, Issue 11, 1986, Pages 996-1000

Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's

Author keywords

Error control coding; hard defects; RAM's; redundancy; reliability; row column replacement; yield improvement

Indexed keywords

DATA STORAGE, SEMICONDUCTOR - STORAGE DEVICES;

EID: 0022812049     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1986.1676701     Document Type: Article
Times cited : (8)

References (13)
  • 1
    • 0020165871 scopus 로고
    • A redundancy circuit for a fault-tolerant 256K MOS RAM
    • Aug.
    • T. Mano et al., “A redundancy circuit for a fault-tolerant 256K MOS RAM,” IEEE J. Solid State Circuits, vol. SC-17, pp. 726–730, Aug. 1982.
    • (1982) IEEE J. Solid State Circuits , vol.SC-17 , pp. 726-730
    • Mano, T.1
  • 2
    • 0018021595 scopus 로고
    • Multiple word/bit line redundancy for semiconductor memories
    • Oct.
    • S. E. Schuster, “Multiple word/bit line redundancy for semiconductor memories,” IEEE J. Solid State Circuits, vol. SC-13, pp. 698–703, Oct. 1978.
    • (1978) IEEE J. Solid State Circuits , vol.SC-13 , pp. 698-703
    • Schuster, S.E.1
  • 3
    • 0018480756 scopus 로고
    • A fault tolerant 64K dynamic random access memory
    • June
    • R. P. Cenker et al., “A fault tolerant 64K dynamic random access memory,” IEEE Trans. Electron. Dev., vol. ED-26, pp. 853–860, June 1979.
    • (1979) IEEE Trans. Electron. Dev. , vol.ED-26 , pp. 853-860
    • Cenker, R.P.1
  • 4
    • 0019624943 scopus 로고
    • Laser programmable redundancy and yield improvement in a 64K DRAM
    • Oct.
    • R. T. Smith, “Laser programmable redundancy and yield improvement in a 64K DRAM,” IEEE J. Solid State Circuits, vol. SC-16, pp. 506–513, Oct. 1981.
    • (1981) IEEE J. Solid State Circuits , vol.SC-16 , pp. 506-513
    • Smith, R.T.1
  • 5
    • 0021444258 scopus 로고
    • Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI
    • June
    • T. E. Mangir, “Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI,” Proc. IEEE, vol. 72, pp. 690–708, June 1984.
    • (1984) Proc. IEEE , vol.72 , pp. 690-708
    • Mangir, T.E.1
  • 6
    • 0019013812 scopus 로고
    • Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product
    • May
    • C. H. Stapper et al., “Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Develop., vol. 24, pp. 398—409, May 1980.
    • (1980) IBM J. Res. Develop. , vol.24 , pp. 398-409
    • Stapper, C.H.1
  • 9
    • 0020821981 scopus 로고
    • On the capacity of computer memory with defects
    • Sept.
    • C. Heegard and A. A. El Gamal, “On the capacity of computer memory with defects,” IEEE Trans. Inform. Theory, vol. IT-29, pp. 731–739, Sept. 1983.
    • (1983) IEEE Trans. Inform. Theory , vol.IT-29 , pp. 731-739
    • Heegard, C.1    El Gamal, A.A.2
  • 10
    • 0018331014 scopus 로고
    • Alpha particle induced soft errors in dynamic memories
    • Jan.
    • T. C. May and M. H. Woods, “Alpha particle induced soft errors in dynamic memories,” IEEE Trans. Electron. Dev., vol. ED-26, pp. 2–9, Jan. 1979.
    • (1979) IEEE Trans. Electron. Dev. , vol.ED-26 , pp. 2-9
    • May, T.C.1    Woods, M.H.2
  • 11
    • 0020193753 scopus 로고
    • Error-correction technique for random access memories
    • Oct.
    • F. I. Osman, “Error-correction technique for random access memories,” IEEE J. Solid State Circuits, vol. SC-17, pp. 877–881, Oct. 1982.
    • (1982) IEEE J. Solid State Circuits , vol.SC-17 , pp. 877-881
    • Osman, F.I.1
  • 12
    • 0020833206 scopus 로고
    • Circuit techniques for a VLSI memory
    • Oct.
    • T. Mano et al., “Circuit techniques for a VLSI memory,” IEEE J. Solid State Circuits, vol. SC-18, pp. 463–469, Oct. 1983.
    • (1983) IEEE J. Solid State Circuits , vol.SC-18 , pp. 463-469
    • Mano, T.1
  • 13
    • 0021502671 scopus 로고
    • A submicron 1 Mbit dynamic RAM with a 4-Bit-at-a-time built-in ECC circuit
    • Oct.
    • J. Yamada et al., “A submicron 1 Mbit dynamic RAM with a 4-Bit-at-a-time built-in ECC circuit,” IEEE J. Solid State Circuits, vol. SC-19, pp. 627–633, Oct. 1984.
    • (1984) IEEE J. Solid State Circuits , vol.SC-19 , pp. 627-633
    • Yamada, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.