Modeling and Analysis of Transient Latchup in Double-Well Bulk CMOS

IEEE Transactions on Electron Devices

Volumn 33, Issue 9, 1986, Pages 1341-1347

  Goto, Gensuke ^a   Takahashi, Hiromasa ^a   Nakamura, Tetsuo ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NOISE, SPURIOUS SIGNAL;

BASE TRANSIT DELAYS; CMOS INTEGRATED CIRCUITS; DOUBLE-WELL BULK CMOS; HIGH-LEVEL CARRIER INJECTION; TRANSIENT LATCHUP;

INTEGRATED CIRCUITS;

EID: 0022787476     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22668     Document Type: Article

References (6)

1. D. B. Estreich and R. W. Dutton, “Modeling latch-up in CMOS integrated circuits,” IEEE Trans. CAD of ICAS, vol. CAD-1, pp. 157—162, Oct. 1982.
2. R. R. Troutman and H. P. Zappe, “A transient analysis of latchup in bulk CMOS,” IEEE Trans. Electron Devices, vol. ED-30, pp. 170–179, Feb. 1983.
3. R. D. Rung and H. Momose, “DC holding and dynamic triggering characteristics of bulk CMOS latchup,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1647–1655, Dec. 1983.
4. T. Aoki, R. Kasai, and S. Horiguchi, “Transient characteristics of latch-up in bulk CMOS,” Electron. Lett., vol. 19, pp. 758–759, Sept. 1983.
5. R. C. Fang and J. L. Moll, “Latchup model for the parasitic p-n-p-n path in bulk CMOS,” IEEE Trans. Electron Devices, vol. ED-31, pp. 113–120, Jan. 1984.
6. L. W. Nagel, “SPICE 2: A computer program to simulate semiconductor circuits,” Memo. ERL-M520, Electron. Res. Lab., Univ. of California, May 1975.