Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

IEEE Transactions on Computers

Volumn C-35, Issue 8, 1986, Pages 742-754

  Reddy, Sudhakar M ^a   Reddy, Madhukar K ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

CMOS logic circuits; stuck open faults; test invalidation; testable designs

Indexed keywords

SEMICONDUCTOR DEVICES, MOS; TRANSISTORS, FIELD EFFECT;

CMOS TECHNOLOGY; STUCK-OPEN FAULTS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0022766854     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1986.1676825     Document Type: Article

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