Analysis and Modeling of Floating-Gate EEPROM Cells

IEEE Transactions on Electron Devices

Volumn 33, Issue 6, 1986, Pages 835-844

  Kolodny, Avinoam ^a   Nieh, Sidney T K ^a   Eitan, Boaz ^b   Shappir, Joseph ^c  

^a INTEL CORPORATION   (United States)

^b WaferScale Integration Inc ^*  (United States)

^c HEBREW UNIVERSITY OF JERUSALEM   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL - NONDESTRUCTIVE; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICES, MOS; SEMICONDUCTOR MATERIALS - CHARGE CARRIERS;

DEEP DEPLETION; FLOATING-GATE EEPROM CELLS; HOLE FLOW; TUNNEL CURRENT; WRITE/ERASE CHARACTERISTICS;

DATA STORAGE, SEMICONDUCTOR;

EID: 0022737546     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22576     Document Type: Article

References (23)

1. W. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. Ranganath, “A 16K bit electrically erasable non-volatile memory,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., p. 152, Feb. 1980.
2. C. Kuo, J. R. Yeargain, W. J. Downey, K. A. Ilgenstein, J. R. Jorvig, S. L. Smith, and A. R. Bormann, “An 80-nS 32-K EEPROM using the FETMOS cell,” IEEE J. Solid-State Circuits, vol. SC-17, p. 821, 1982.
3. G. Yaron, S. J. Prasad, M. S. Ebel, and B. M. K. Leong, “A 16K EEPROM employing new array architecture and designed-in reliability features,” IEEE J. Solid-State Circuits, vol. SC-17, p. 833, 1982.
4. A. Gupta, T. L. Chiu, M. S. Chang, A. Renninger, and G. Perlegos, “A 5V-only 16K EEPROM utilizing oxynitride dielectrics and EPROM redundancy,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., p. 184, Feb. 1982.
5. T. Hogiwara, Y. Yatsuda, R. Kendo, S. I. Minami, T. Aoto, and Y. Itoh, “A 16 Kbit electrically erasable PROM using n-channel Si-gate MNOS technology,” IEEE J. Solid-State Circuits, vol. SC-15, p. 346, 1980.
6. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO,” J. Appl. Phys., vol. 40, p. 278, 1969.
7. Z. A. Weinberg, “On tunneling in metal-oxide-silicon structures,” J. Appl. Phys., vol. 53, p. 5052, 1982.
8. B. Euzent, N. Boruta, J. Lee, and C. Jenq, “Reliability aspects of a floating gate EEPROM,” in Proc. Int. Reliability Physics Symp., 1981.
9. P. I. Suciu, B. P. Cox, D. D. Rinerson, and S. F. Cagnina, “Cell model for EEPROM floating-gate memories,” in IEDM Tech. Dig. (San Francisco), p. 737, 1982.
10. S. T. Wang, “Charge retention of floating-gate transistors under applied bias conditions,” IEEE Trans. Electron Devices, vol. ED-27, p. 297, 1980.
11. L. D. Yau, “A simple theory to predict the threshold voltage of short channel IGFET's,” Solid-State Electron., vol. 17, pp. 1059–1063, 1974.
12. Y. Nissan-Cohen, D. Frohman-Bentchkowsky, and J. Shappir, “Characterization of simultaneous bulk and interface high-field trapping effects in SiO 2,” in IEDM Tech. Dig. (Washington. DC), paper 8.2, 1983.
13. M. Itsumi, “Positive and negative charging of thermally grown Si0 2 induced by Fowler-Nordheim emission,” J. Appl. Phys., vol. 52. pp. 3491–3497, 1981.
14. E. H. Nicollian and J. R. Brewz, MOS Physics and Technology. New York: Wiley, 1982, ch. 9.
15. E. Suzuki and Y. Hayashi, “Transport processes of electrons in MNOS structures,” Appl. Phys., vol. 50, pp. 7001–7006, 1979.
16. M. S. Liang, C. Chang, Y. T. Yeow, C. Hu, and R. W. Brodersen, “Creation and termination of substrate deep depletion in thin oxide MOS capacitors by charge tunneling,” IEEE Electron Device Lett., vol. EDL-4, pp. 350–352, 1983.
17. E. O. Kane, “Electron scattering by pair production in silicon,” Phys Rev., vol. 159, pp. 624–631, 1967.
18. B. Eitan and A. Kolodny, “Two components of tunneling current in metal-oxide-semiconductor structures,” Appl. Phys. Lett., vol. 43, pp. 106–108, 1983.
19. J. M. Aitken and D. R. Young, “Avalanche injection of holes into SiO 2,” IEEE Trans. Nucl. Sci., vol. NS-24, pp. 2128–2134, 1977.
20. C. Jenq et al., “High-field generation of electron traps and charge trapping in ultra-thin SiO 2,” in IEDM Tech. Dig., pp. 388–391, 1981.
21. Y. Tarui, Y. Hayashi, and K. Nagai, “Electrically programmable nonvolatile semiconductor memory,” in Proc. 5th Conf. Solid State Devices, supplement to J. Japan Soc. Appl. Phy., vol. 43, 1974.
22. Y. N. Hsieh, R. A. Wood, and P. O. Wang, “Electrically alterable programmable logic array,” in IEDM Tech. Dig., pp. 598–601, 1980.
23. H. Schaver et al., “A high-density, high performance EEPROM cell,” IEEE Trans. Electron Devices, vol. ED-29, p. 1178, 1982.