A Methodology for Worst-Case Analysis of Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 5, Issue 1, 1986, Pages 104-113

  Nassif, Sani R ^a   Strojwas, Andrzej J ^a   Director, Stephen W ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN - ANALYSIS; COMPUTER SOFTWARE - SOFTWARE ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; STATISTICAL METHODS;

FLUCTUATIONS IN IC MANUFACTURING; WORST-CASE ANALYSIS SOFTWARE PACKAGE;

INTEGRATED CIRCUITS;

EID: 0022603501     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270181     Document Type: Article

References (4)

1. D. A. Divekar, “DC statistical circuit analysis for bipolar IC's using parameter correlations—An experimental example,” IEEE Trans. Computer-Aided Design, vol. CAD-3, Jan. 1984.
2. W. Maly and A. J. Strojwas, “Statistical Simulation of the IC Manufacturing Process,” IEEE Trans. Computer-Aided Design, vol. CAD-1, July 1982.
3. S. R. Nassif, A. J. Strojwas, and S. W. Director. “FABRICS II—A statistically based IC fabrication process simulator,” IEEE Trans. Comput-Aided Design, vol. CAD-3, Jan. 1984.
4. C. J. Spanos, “Statistical parameter extraction for IC process characterization,” Ph. D. dissertation, Carnegie-Mellon Univ., Pittsburgh, PA, 1985.