VLSI Yield Prediction and Estimation: A Unified Framework

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 5, Issue 1, 1986, Pages 114-130

  Maly, Wojciech ^a   Strojwas, Andrzej J ^a   Director, Stephen W ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - MANUFACTURE; STATISTICAL METHODS;

VLSI YIELD PREDICTION/ESTIMATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0022583080     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270182     Document Type: Article

References (62)

1. K. J. Antreich and R. K. Koblitz, “Design centering by yield prediction,” IEEE Trans. Circuits Syst., vol. CAS-29, pp. 88–95. Feb. 1982.
2. Y. Aoki, T. Toyabc, S. Asai, and T. Hagiwara, “CASTAM: A process variation analysis simulator for MOS LSI’s,” IEEE Trans. Electron Devices, vol. ED-31, 1462 1467,1984.
3. P. Balaban and J. J. Golembeski. “Statistical analysis for practical circuit design,” IEEE Trans. Circuits Syst., vol. CAS-22, pp. 100–108, Feb. 1975.
4. J. W. Bandler and H. L. Abdel-Malek, “Optimal centering, tolerancing, and yield determination via updated approximations and cuts,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 853–871, Oct. 1978.
5. J. Bernard, “The IC yield problem: A tentative analysis for MOS/SOS circuits,” IEEE Trans. Electron Devices, vol. ED-25, pp. 939–944, Aug. 1978.
6. R. K. Brayton, S. W. Director, and G. D. Hachtel, “Yield maximization and worst-case design with arbitrary statistical distributions,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 756–764, Sept. 1980.
7. I-hao Chen and A. J. Strojwas, “A methodology for optimal test structure design,” in Proc. of CICC 85, pp. 520–523, Portland, 1985.
8. P. Cox, P. Yang, and P. Chatterjee, “Statistical modeling for efficient parametric yield estimation,” in Proc. Int. Electron Device Meeting, pp. 242-245,1984.
9. S. W. Director and G. D. Hachtel, “The simplicial approximation approach to design centering,” IEEE Trans. Circuits Syst., vol. CAS 24, pp. 363–372, July 1977.
10. S. W. Director, G. D. Hachtel, and L. M. Vidigal, “Computationally efficient yield estimation procedures based on simplicial approximation,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 121–130, Mar. 1978.
11. A. V. Ferris-Prabhu, “Modeling of critical area in yield forecasts,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 874–878, Aug. 1985.
12. A. V. Ferris-Prabhu, “Defect size variations and their effect on the critical area of VLSI devices,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 878–880, Aug. 1985.
13. S. K. Ghandhi, VLSI Fabrication Principles. New York: Wiley, 1983.
14. D. J. Giannopoulos and S. W. Director, “IC Fabrication Process Optimization,” in Proc. of ICCAD-84, pp. 164–166. Santa Clara, CA, November 1984.
15. A. Gupta, W. A. Porter, and J. W. Lathrop, “Defect analysis and yield degradation of integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 96–103. June 1974.
16. P. Kager and A. J. Strojwas, “PI/C: process interpreter/compiler,” in Proc. of ICCAD 85, Santa Clara, CA, 1985.
17. D. P. Kennedy, P. C. Murley, and R. R. O’Brien, “A statistical approach to the design of diffused junction transistors,” IBM J. Res. Develop., vol. 8, no. 5, pp. 482–495, Nov. 1964.
18. W. Kuzmicz, “Modeling of minority carrier current in heavily doped regions with application to bipolar IC simulation,” in Proc. of IC CAD-84, pp. 182–184, Santa Clara, CA, 1984.
19. M. R. Lightner and S. W. Director, “Multiple criterion optimization with yield maximization,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 781–790, Aug. 1981.
20. W. Maly, A. J. Strojwas, and S. W. Director, “Fabrication based statistical design of monolithic IC’s,” in Proc. ISCAS, pp. 135–138, Chicago, IL, Apr. 1981.
21. W. Maly, J. Gempel, D. Korzec, A. P. Piotrowski, and M. Syrzycki, “Statistical simulation of VLSI IC cell,” in Proc. ICCAD-83, pp. 254–255. Santa Clara, CA, Sept. 1983.
22. W. Maly and Z. Pizlo, “Tolerance assignment for IC selection tests,- IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 156–162, Apr. 1985.
23. r231 W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 166–177, July 1985.
24. Modeling of random phenomena in CAD of 1C—A basic the-oretical consideration,” in Proc. of ISCAS 85, pp. 427–430, Kyoto, Japan, 1985.
25. W. Maly and J. Deszczka, “Yield estimation model for VLSI artwork evaluation,” Electron. Lett., vol. 19, no. 6, pp. 226–227, Mar. 1983.
26. W. Maly and S. W. Director, “Dimension reduction procedure for simplicial approximation approach to design centering,” Proc. Inst. Elect. Eng., vol. 127, no. 6, pp. 255–259, Dec. 1981.
27. W. Maly, J. Ferguson, and J. P. Shen, “Systematic characterization of physical defects for fault analysis of MOS IC cells,” in Proc. Int. Test Conf., 1984. Philadelphia, PA, Oct. 1984.
28. W. Maly and T. Gutt, “Simulation of quality control system applied in silicon IC technology,” in Simulation of Control Systems, I. Troch (Ed.), The Netherlands: North Holland, 1978.
29. W. Maly and A. J. Strojwas, “Statistical simulation of the IC manufacturing process,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 120–131, July 1982.
30. “Simulation of bipolar elements for statistical circuit design,” in Proc. ISCAS, pp. 788–791, Tokyo, Japan, July 1979.
31. T. E. Mangir, “Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Source of failures and yield improvements for VLSI,” in Proc. IEEE, vol. 72, 690–708, June 1984.
32. G. E. Moore, “A simple method for modeling VLSI yields,” Electronics, vol. 43. pp. 126–130, 1970.
33. B. T. Murphy, “Cost-size optima of monolithic integrated circuits,” Proc. IEEE, vol. 52, 1537–1545, Dec. 1964.
34. S. R. Nassif, A. J. Strojwas, and S. W. Director, “FABRICS II: A statistically based IC fabrication process simulator,” IEEE Trans. Computer-Aided Design, vol. CAD-3, 20–46, Jan. 1984.
35. P. Odryna and A. J. Strojwas, “PROD: A VLSI fault diagnosis system,” IEEE Design & Test of Computers. Dec. 1985.
36. T. Okabe et al., “A simple method for modeling VLSI yields,” Elec. Eng. Japan, vol. 92: pp. 135–141, 1972.
37. O. Paz and T. Lawson. Jr., “Modification of Poisson statistics: Modeling defects induced by diffusion,” IEEE J. Solid-State Circuits, vol. SC-12, 540–546, Oct. 1977.
38. J. F. Pinel and K. Singhal, “Efficient Monte Carlo Computation of circuit yield using importance sampling,” in Proc. of ISCAS 77, pp. 575–578, 1977.
39. E. Polak and A. Sangiovanni-Vincentelli, “Theoretical and computational aspects of the optimal design centering, tolerancing, and tuning problem,” IEEE Trans. Circuits Syst., vol. CAS-26, pp. 795–813, Sept. 1979.
40. P. J. Rankin, “Statistical modeling for integrated circuits,” IEE Proc., G, vol. 129, pp. 186–191, Aug. 1982.
41. K. V. Ravi, Imperfections and Impurities in Semiconductor Silicon. New York: 1981.
42. R. Razdan and A. J. Strojwas, “Statistical design rule developer,” in Proc. of ICCAD 85, Santa Clara, CA, 1985.
43. M. J. Saccamango and A. J. Strojwas, “Analytical modeling of small-geometry MOSFET’s,” in ICCAD Dig. Tech. Papers, pp. 170–172, 1984.
44. K. A. Sakallah and S. W. Director, “SAMSON2: An event driven VLSI circuit simulator,” Research Rep. CMUCAD-84-37, SRC-CMU Center for Computer-Aided Design, Dep. of Elect. and Comp. Engineering, Carnegie-Mellon Univ., Sept. 1984.
45. J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design & Test, Dec. 1985.
46. C. J. Spanos and S. W. Director, “PROMETHEUS: A program for VLSI process parameters extraction,” in Proc. of ICCAD-83, pp. 176–177, Santa Clara, CA, Sept. 1983.
47. C. H. Stapper, “Defect density distribution for LSI yield calculations,” IEEE Trans. Electron Devices, vol. ED-20, pp. 655–657, July 1973.
48. —, “On a composite model to the IC yield problem,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 537–539, Dec. 1975.
49. C. H. Stapper et al., “Yield modeling for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Develop., vol. 24(3), pp. 398–409, May 1980.
50. Ch. H. Stapper, “Yield model for 256K RAMs and beyond,” in Proc. of 1982 Int. Solid-State Circuits Conf., pp. 12–13, 1982.
51. A. J. Strojwas and S. W. Director, “A pattern recognition based meth o d for IC failure analysis,” IEEE Trans. Computer-Aided Design, vol. CAD-4, Jan. 1985.
52. A. J. Strojws, S. R. Nassif, and S. W. Director, “Optimal design of VLSI minicells using a statistical process simulator, in Proc. 1983 ISCAS, Jan. 1983.
53. —, “A methodology for worst case design of integrated circuits,” in Proc. of ICCAD-83, Sept. 1983.
54. A. J. Strojwas and Z. Li, “Bipolar device models in the statistical process/device simulator FABRICS II. in Proc. of ICCAD 84, pp. 185–187, Santa Clara, CA, 1984.
55. A. J. Strojwas, “CMU-CAM system,” in Proc. of 22-nd DA Conf., pp. 319–325, Las Vegas, NV. 1985.
56. A. J. Strojwas, S. R. Nassif, and S. W. Director, “A methodology for worst case design of integrated circuits,” in Proc. of ICCAD-83, pp. 152–153, Santa Clara, CA, 1983.
57. A. J. Strojwas,, “A pattern recognition based system for IC failure analysis,” Ph.D. dissertation, Carnegie-Mellon Univ., Sept. 1982.
58. M. A. Styblinski and L. J. Opalski, “Random perturbation method for IC yield optimization with deterministic process parameters,” in Proc. of ICCAD-84, pp. 977–980, Santa Clara, CA, Nov. 1984.
59. S. M. Sze, VLSI Technology. New York: McGraw-Hill, 1983.
60. K. S. Tahim and R. Spence, “A radial exploration approach to manufacturing yield estimation and design centering,” IEEE Trans. Circuits Syst., vol. CAS-26, pp. 768–774, Sept. 1979.
61. H. Walker and S. W. Director, “Yield simulation for integrated circuits,” in Proc. of ICCAD-83, pp. 256–257, Santa Clara, CA, Sept. 1983.
62. R. M. Warner, Jr., “Applying a composite model to the IC yield problem,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 86–95, June 1974.