Optimum Design of Dual-Control Gate Cell for High-Density EEPROM's

IEEE Transactions on Electron Devices

Volumn 32, Issue 9, 1985, Pages 1776-1780

  Eda, Katsuhiko Hi ^a   Wada, Masashi ^a   Shibata, Tadashi ^a   Inoue, Satoshi ^a   Momodomi, Masaki ^a   Iizuka, Hisakazu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN - OPTIMIZATION; LOGIC DEVICES - GATES;

DUAL-CONTROL GATE CELL; ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM); FLOATING GATE-TYPE CELL; HALF-SELECTION MODE OPERATION; WRITE/ERASE ENDURANCE;

DATA STORAGE UNITS;

EID: 0022115427     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.22196     Document Type: Article

References (12)

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