VLSI Array Processors

IEEE ASSP Magazine

Volumn 2, Issue 3, 1985, Pages 4-22

  Kung, S Y ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM MAPPINGS; COMMUNICATION CONSTRAINTS; SYSTOLIC ARRAYS; VLSI ARRAY PROCESSORS; WAVEFRONT ARRAYS;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING - ALGORITHMS; COMPUTER SYSTEMS, DIGITAL - REAL TIME OPERATION; IMAGE PROCESSING; INTEGRATED CIRCUITS, VLSI;

SIGNAL PROCESSING;

EID: 0022092257     PISSN: 07407467     EISSN: None     Source Type: Journal    
DOI: 10.1109/MASSP.1985.1163741     Document Type: Article

References (21)

1. Burg, J. P. Maximum Entropy Spectral Analysis. PhD thesis, Stanford University, 1975.
2. Capon, J. (1969), “High-Resolution Frequency-Wavenumber Spectrum Analysis,” Proc. IEEE, 57, 1408–1418.
3. Chase, M. (1984), “A Pipelined Data Flow Architecture for Digital Signal Processing the NEC μPD7281,” IEEE Workshop on VLSI Signal Processing, Los Angeles, Nov. 1984.
4. Davis, R. H., and Thomas, D. (1984), “Systolic array chip matches the pace of high-speed processing,” Electronic design, Vol.: 207–218, October, 1984.
5. Dennis, J. B. (1980), “Data Flow Supercomputers,” IEEE Computer, Nov, 1980, 48–56.
6. Fisher, A. L., and Kung, H.T. (1985), “Special-purpose VLSI Architectures: General Discussions and a Case Study,” In VLSI and Modern Signal Processing, Kung, S.Y., Whitehouse, H.J., and Kailath, T. K. (eds.) Prentice-Hall, Inc.
7. Gentleman, W.M., and Kung, H.T. (1981), “Matrix Triangularization by Systolic Array,” SPIE Proc. Real-Time Signal Processing IV 298.
8. Hayes, J. P. (1978). Computer Architecture and Organization. McGraw Hill, N.Y.
9. Kung, S.Y., (1984), “On Supercomputing with Systolic/Wavefront Array Processors,” Proceedings of the IEEE, Vol. 72(7).
10. Kung, H.T., and Leiserson, C. E. (1978), “Systolic Arrays (for VLSI),” Sparse Matrix Symposium, SIAM, 256–282.
11. Kung, S.Y., Arun, K.S., Gal-Ezer, R.J., and Bhaskar Rao, D. V. (1982), “Wavefront Array Processor: Language, Architecture, and Applications,” IEEE Transactions on Computers, Special Issue on Parallel and Distributed Computers C-31 (11): 1054–1066.
12. Kung, S.Y., and Hu, Y.H. (1983), “A Highly Concurrent Algorithm and Pipelined Architecture for Solving Toeplitz Systems,” IEEE Transactions on ASSP, ASSP-31 (No. 1)66–76.
13. Kung, S. Y., and Lo, S. C. (1985), “A Spiral Systolic Architecture/Algorithm for Transitive Closure Problems,” Submitted to IEEE Trans. on Computers, Special Issue on Distributed Computing, Vol. C-34(12).
14. Mason, S.J. (1953), “Feedback Theory—Some Properties of Signal Flow Graphs,” Proceedings, IRE, 41: 920–926.
15. McWhirter, J.G. (1983), “Recursive least-squares minimization using a systolic array,” Real Time Signal Processing VI, 105.
16. Broomhead, D. S., et al. (1984), “A Practical Comparison of the Systolic and Wavefront Array Processing Architectures,” Proceedings, IEEE Workshop on VLSI Signal Processing, Los Angeles, November, 1984.
17. Mead, C., and Conway, L. (1980). Introduction to VLSI Systems, Addison-Wesley.
18. Seitz, C. (1984), “Concurrent VLSI Architectures,” IEEE Transactions on Computer, C-33.
19. Stewart, G.W. (1973). Introduction to Matrix Computations, Academic Press.
20. Ware, F., et al. (1984), “Fast 64-bit chip set gangs up for double-precision floating-point work,” Electronics, 99–103, July, 1984.
21. Wilson, P., (1984), “Thirty-two bit micro supports multiprocessing,” Computer Design, 143–150. June, 1984.