NMOS Protection Circuitry

IEEE Transactions on Electron Devices

Volumn 32, Issue 5, 1985, Pages 910-917

  Rountree, Robert N ^a   Hutchins, Charles L ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES - PROTECTION; ELECTROSTATICS; INTEGRATED CIRCUITS - FAILURE;

BREAKDOWN PHENOMENA; ELECTROSTATIC DISCHARGE PROTECTION; PROTECTION-CIRCUIT DESIGN;

SEMICONDUCTOR DEVICES, MOS;

EID: 0022061460     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.22047     Document Type: Article

References (8)

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2. W. J. Orvis, C. F. McConaghy, J. H. Yee, G. H. Khanaka, L. C. Martin, and D. L. Lair, “Modeling and testing for second breakdown phenomena,” in Electric. Overstress/Electrostat. Discharge Symp. Proc., vol. EOS-5, pp. 108–117, Sept. 1983.
3. L. F. DeChiaro, “Electro-thermomigration in NMOS LSI devices,” in Proc. IRPS, pp. 223–229, June 1981.
4. A. Christou, “Electro-thermomigration in Al/Si, Au/Si interdigitized ized test structures,” J. Appl. Phys., vol. 44, no. 7, pp. 2975–2979, July 1973.
5. M. S. Ash, “Non-linear kinetics of semiconductor junction thermal failure,” in Electric. Overstress/Electrostat. Discharge Symp. Proc., vol. EOS-3, pp. 242–245, Sept. 1981.
6. W. B. Smith, D. H. Pontius, and P. P. Budenstein, “Second breakdown and damage in junction devices,” IEEE Trans. Electron Devices, vol. ED-20, no. 8, pp. 731–743, Aug. 1973.
7. N. Kusnezov and J. Smith, “Modeling of EOS in silicon devices,” in Electric. Overstress/Electrostat. Discharge Symp. Proc., vol. EOS-3, pp. 132–138, Sept. 1981.
8. C. Duvvury, R. N. Rountree and L. S. White, “A summary of most effective electrostatic discharge protection circuits for MOS memories and their observed failure modes,” in Electric. Overstress/ Electrostat. Discharge Symp. Proc., vol. EOS-5, pp. 181–184, Sept. 1983.