Tolerance Assignment for IC Selection Tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 4, Issue 2, 1985, Pages 156-162

  Maly, Wojciech ^a   Pizlo, Zygmunt ^a,b  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b INSTITUTE OF FUNDAMENTAL TECHNOLOGICAL RESEARCH   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED MANUFACTURING - TESTING; MATHEMATICAL STATISTICS; PROCESS CONTROL;

IC SELECTION TESTS; SELECTION THRESHOLDS; TOLERANCE ASSIGNMENT;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0022046191     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1985.1270109     Document Type: Article

References (6)

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2. [2] D. R. Cox, Planning of Experiments. New York: Wiley, 1958.
3. [3] J. D. Finn, A General Model for Multivariate Analysis. Holt Rinehart and Winston, 1974.
4. [4] J. Kiefer and J. Wolfowitz, “Optimum designs in regression problems,” Ann.Math. Stat., vol. 30, no. 2, pp. 271–294, 1959.
5. [5] W. Maly and T. Gutt, “Simulation of quality control system applied in silicon IC technology,” in Simulation of Control Systems, (I. Troch, Ed.), The Netherlands: North Holland, 1978.
6. [6] W. Maly and A. J. Strojwas, “Statistical simulation of the IC manu facturing process,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 120–131, July 1982.