A Direct Measurement Technique for Small Geometry MOS Transistor Capacitances

IEEE Electron Device Letters

Volumn 6, Issue 1, 1985, Pages 40-42

  Weng, K C K ^a   Yang, P ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC MEASUREMENTS - CAPACITANCE; INTEGRATED CIRCUITS; TRANSISTORS;

MOS TRANSISTOR CAPACITANCES; MOSFET INTRINSIC CAPACITANCES;

SEMICONDUCTOR DEVICES, MOS;

EID: 0021787638     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1985.26035     Document Type: Article

References (5)

1. P. Yang and P. K. Chatterjee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-1, p. 169, 1982.
2. J. J. Paulos, D. A. Antoniadis, and Y. P. Tsividis, “Measurement of intrinsic capacitances of MOS transistors,” in ISSCC Dig. Tech. Papers, p. 238, 1982.
3. H. Iwai, J. Oristian, J. Walker, and R. Dutton, “Small geometry MOS transistor measurements and observed short and narrow channel effects,” VLSI Symp. Technol. (San Diego, CA, Sept. 1984).
4. E. W. Greeneich, “An analytical model for the gate capacitance of small-geometry MOS structures,” IEEE Trans. Electron Devices, vol. ED-30, p. 1838, 1983.
5. P. Yang, B. D. Epler, and P. K. Chatterjee, “An investigation of the charge conservation problem for MOSFET circuit simulation,” IEEE J. Solid-State Circuits, vol. SC-18, p. 128, 1983.