Si BIPOLAR MULTI-Gbit/s LOGIC FAMILY USING SUPER SELF-ALIGNED PROCESS TECHNOLOGY.

Conference on Solid State Devices and Materials

Volumn , Issue , 1984, Pages 217-220

  Ichino, Haruhiko ^a   Suzuki, Masao ^a   Hagimoto, Kazuo ^a   Konaka, Shinsuke ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES - DESIGN;

CIRCUIT PARAMETERS OPTIMIZATION; SILICON BIPOLAR LOGIC FAMILY; SUPER SELF-ALGINED PROCESS TECHNOLOGY; TRANSISTOR SIZE OPTIMIZATION;

LOGIC CIRCUITS;

EID: 0021631501     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7567/ssdm.1984.a-4-4     Document Type: Conference Paper

References (3)