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Volumn 31, Issue 4, 1984, Pages 694-717

Configuration of VLSI Arrays in the Presence of Defects

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0021508867     PISSN: 00045411     EISSN: 1557735X     Source Type: Journal    
DOI: 10.1145/1634.2377     Document Type: Article
Times cited : (85)

References (28)
  • 1
    • 0017981717 scopus 로고
    • Wafer-scale integration-A fault tolerant procedure.
    • (June)
    • Aubusson, R., and Catt, I. Wafer-scale integration-A fault tolerant procedure. IEEE J Solid-State Circuits SC-13, 3 (June 1978), pp. 339-344.
    • (1978) IEEE J Solid-State Circuits , vol.SC-13 , Issue.3 , pp. 339-344
    • Aubusson, R.1    Catt, I.2
  • 2
    • 84915211389 scopus 로고
    • A critique and appraisal of VLSI models of computation.
    • H.T. Kung, B. Sproull, and G. Steele, Eds. Computer Science Press, Rockville, Md.
    • Bilardi, G., Pracchi, M., and Preparata, F. A critique and appraisal of VLSI models of computation. In VLSI Systems and Computation, H.T. Kung, B. Sproull, and G. Steele, Eds. Computer Science Press, Rockville, Md., 1981, pp. 81-88.
    • (1981) In VLSI Systems and Computation , pp. 81-88
    • Bilardi, G.1    Pracchi, M.2    Preparata, F.3
  • 10
    • 84976799954 scopus 로고    scopus 로고
    • Configuration of VLSI arrays in the presence of defects-Part II
    • (See also [9]).
    • Greene, J.W., and El Gamal, A. Configuration of VLSI arrays in the presence of defects-Part II. Submitted for publication. (See also [9]).
    • Submitted for publication
    • Greene, J.W.1    El Gamal, A.2
  • 11
    • 3042582096 scopus 로고
    • Bomes supérieures de la probabilité critique dans un processus de filtration.
    • Centre National de la Recherche Scientifique, Paris, France
    • Hammersley, J.M. Bomes supérieures de la probabilité critique dans un processus de filtration. In Le Calcul des Probability el ses Applications. Centre National de la Recherche Scientifique, Paris, France, 1959, pp. 17-37.
    • (1959) In Le Calcul des Probability el ses Applications. , pp. 17-37
    • Hammersley, J.M.1
  • 12
    • 0002446794 scopus 로고
    • A lower bound for the critical probability in a certain percolation process.
    • Harris, T. A lower bound for the critical probability in a certain percolation process. Proc. Cambridge Phil Soc. 56(1960), 13-20.
    • (1960) Proc. Cambridge Phil Soc. , vol.56 , pp. 13-20
    • Harris, T.1
  • 13
    • 84910592133 scopus 로고
    • Wafer scale integration of configurable, highly parallel (CHiP), processors (extended abstract).
    • (Bellaire, Mich., Aug. 24-27). IEEE, New York
    • Hedlund, K., and Snyder, L. Wafer scale integration of configurable, highly parallel (CHiP), processors (extended abstract). In Proceedings of the International Conference on Parallel Processing (Bellaire, Mich., Aug. 24-27). IEEE, New York, 1982, pp. 262-264.
    • (1982) In Proceedings of the International Conference on Parallel Processing , pp. 262-264
    • Hedlund, K.1    Snyder, L.2
  • 14
    • 0019286377 scopus 로고
    • Adaptive wafer scale integration
    • Supp. 19-1
    • Hsia, Y., Chang, G., and Erwin, F. Adaptive wafer scale integration. Jpn. J. App. Phys. 19, Supp. 19-1 (1980), 193-202.
    • (1980) Jpn. J. App. Phys. , vol.19 , pp. 193-202
    • Hsia, Y.1    Chang, G.2    Erwin, F.3
  • 15
    • 0019892884 scopus 로고
    • A reconfigurable and fault tolerant VLSI multiprocessor array.
    • (Minneapolis, Minn., May 12-14). IEEE, New York
    • Koren, I. A reconfigurable and fault tolerant VLSI multiprocessor array. In Proceedings of the 8th Annual Symposium on Computer Architecture (Minneapolis, Minn., May 12-14). IEEE, New York, 1981, pp. 425-442.
    • (1981) In Proceedings of the 8th Annual Symposium on Computer Architecture , pp. 425-442
    • Koren, I.1
  • 19
    • 0020151818 scopus 로고
    • Fault tolerant design for VLSI: Effect of interconnect requirements on yield improvement of VLSI designs.
    • (July)
    • Mangir, T., and Avizienis, A. Fault tolerant design for VLSI: Effect of interconnect requirements on yield improvement of VLSI designs. IEEE Trans Comput C-31, 7 (July 1982), 609-616.
    • (1982) IEEE Trans Comput , vol.C-31 , Issue.7 , pp. 609-616
    • Mangir, T.1    Avizienis, A.2
  • 20
    • 0012604088 scopus 로고
    • An approach to highly integrated computer-maintained cellular arrays.
    • (June)
    • Manning, F. An approach to highly integrated computer-maintained cellular arrays. IEEE Trans. Comput., 6 (June 1977), 536-552.
    • (1977) IEEE Trans. Comput , Issue.6 , pp. 536-552
    • Manning, F.1
  • 22
    • 84976701375 scopus 로고
    • 2nd ed. Holt, Rinehart & Winston, New York, 190.
    • Pen nisi, L. Elements of Complex Variables, 2nd ed. Holt, Rinehart & Winston, New York, 1976, pp. 177-178, 190.
    • (1976) Elements of Complex Variables , pp. 177-178
    • Pen nisi, L.1
  • 23
    • 84915615955 scopus 로고
    • On the use of nonvolatile programmable links for restructurable VLSI.
    • (Pasadena, Calif., Jan. 22-24). Caltech, Pasadena, Calif
    • Raffel, J. On the use of nonvolatile programmable links for restructurable VLSI. In Proceedings of the Caltech Conference on Very Large Scale Integration (Pasadena, Calif., Jan. 22-24). Caltech, Pasadena, Calif,, 1979, pp. 95-104.
    • (1979) In Proceedings of the Caltech Conference on Very Large Scale Integration , pp. 95-104
    • Raffel, J.1
  • 24
    • 84976831915 scopus 로고
    • The Diogenes approach to testable fault-tolerant networks of processors.
    • Computer Science Dept., Duke Univ., Durham, N.C., May
    • Rosenberg, A. The Diogenes approach to testable fault-tolerant networks of processors. Rep. CS-1982-6.1, Computer Science Dept., Duke Univ., Durham, N.C., May 1982.
    • (1982) Rep. CS-1982-6.1
    • Rosenberg, A.1
  • 28


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.