Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 4, Issue 4, 1985, Pages 561-574

  Sangiorgi, Enrico C ^a   Pinto, Mark R ^a   Swirhun, Stanley E ^b   Dutton, Robert W ^b  

^a STANFORD UNIVERSITY   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; MATHEMATICAL MODELS;

CMOS INTEGRATED CIRCUITS; LATCHUP ANALYSIS; TRENCHED SCHOTTKY PMOS; VLSI CMOS TECHNOLOGY;

INTEGRATED CIRCUITS, VLSI;

EID: 0021508184     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1985.1270158     Document Type: Article

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