Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices

Solid State Electronics

Volumn 27, Issue 10, 1984, Pages 899-906

  Bhattacharyya, Anjan ^a  

^a Philips Signetics Company   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES - GATES; SEMICONDUCTOR DEVICES - MODELING; SEMICONDUCTOR MATERIALS - CHARGE CARRIERS;

CHARGE RETENTION; FLOATING GATE EEPROM DEVICES; WRITE/ERASE CYCLES;

DATA STORAGE, SEMICONDUCTOR;

EID: 0021505267     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(84)90009-1     Document Type: Article

References (8)

1. Fowler-Nordheim Tunneling into Thermally Grown SiO2
2. Charge retention of floating-gate transistors under applied bias conditions