Latchup Suppression in Fine-Dimension Shallow p-Well CMOS Circuits

IEEE Transactions on Electron Devices

Volumn 31, Issue 10, 1984, Pages 1472-1481

  Lewis, Alan G ^a  

^a Hirst Research Centre   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS - PERFORMANCE;

LATCHUP SUPPRESSION; P-WELL CMOS CIRCUITS; VLSI CMOS;

INTEGRATED CIRCUITS, VLSI;

EID: 0021501551     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21735     Document Type: Article

References (7)

1. A. G. Lewis and S. L. Partridge, “Shallow p-wells for fine-dimension CMOS circuits,” IEEE Trans. Electron Devices, vol. ED-30, no. 12, pp. 1680–1693, 1983.
2. A. Ochoa, W. Dawes, and D. Estreich, “Latchup control in CMOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-26, no. 6, pp. 5065–5068, 1979.
3. P. V. Dressendorfer and A. Ochoa, “An analysis of the modes of operation of parasitic SCR's,” IEEE Trans. Nucl. Sci., vol. NS-28, no. 6, pp. 4288–4291, 1981.
4. R. D. Rung, C. J. Dell'Oca, and L. C. Walker, “A retrograde p-well for higher density CMOS,” IEEE Trans. Electron Devices, vol. ED-28, no. 10, pp. 1115–1119, 1981.
5. R. R. Troutman and H. P. Zappe, “A transient analysis of latchup in bulk CMOS,” IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 170–179, 1983.
6. A. W. Wieder, C. Werner, and J. Harter, “Design model for bulk CMOS scaling enabling accurate latchup prediction,” IEEE Trans. Electron Devices, vol. ED-30, no. 3, pp. 240–245, 1983.
7. A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted (100) Si surface,” in IEDM Tech. Dig., pp. 18–21, Dec. 1979.