Systolic Multipliers for Finite Fields GF(2m)

IEEE Transactions on Computers

Volumn C-33, Issue 4, 1984, Pages 357-360

  Yeh, C S ^a   Reed, Irving S ^a   Truong, T K ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Finite field; logic design; primitive element; systolic array

Indexed keywords

COMPUTERS, DIGITAL;

EID: 0021411526     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1984.1676441     Document Type: Article

References (11)

1. P. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. Amsterdam: North-Holland, 1978.
2. W. W. Peterson and E.J. Weldon, Jr., Error-Correcting Codes, 2nd ed. Cambridge, MA: MIT Press, 1972.
3. E. R. Berlekamp, Algebraic Coding Theory. New York: McGraw-Hill, 1968.
4. B. Benjauthrit and I. S. Reed, “Galois switching functions and their applications,” IEEE Trans. Comput., vol. C-25, pp. 78–86, Jan. 1976.
5. I.S. Reed and T. K. Truong, “The use of finite fields to compute convolutions,” IEEE Trans. Inform. Theory, vol. IT-21, no. 2, pp. 208–213, Mar. 1975.
6. T. C. Bartee and D.I. Schneider, “Computation with finite fields,” Inform. Contr., vol. 6, pp. 79–98, Mar. 1963.
7. B.A. Laws and C. K. Rushforth, “A cellular-array multiplier for GF(2m),” IEEE Trans. Comput., vol. C-20, pp. 1573–1578, Dec. 1971.
8. R.G. Gallagher, Information Theory and Reliable Communication. New York: Wiley, 1968.
9. H.T. Kung, “Why systolic architectures?” IEEE Computer, vol. 15, 37–46, Jan. 1982.
10. R.F. Lyon, “Two’s complement pipeline multipliers,” IEEE Trans. Commun., vol. COM-24, pp. 418–425, Apr. 1976.
11. J.V. McCanny and J.G. McWhirter, “Completely iterative pipelined multiplier array suitable for VLSI,” IEE Proc. G, Electronic Circuits and Systems, vol. 129, no. 2, pp. 40–46, Apr. 1982.