Coupling Effects in the Time Domain for an Interconnecting Bus in High-Speed GaAs Logic Circuits

IEEE Transactions on Electron Devices

Volumn 31, Issue 3, 1984, Pages 347-352

  Chilo, Jean ^a   Arnaud, Thierry ^a  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI;

LOGIC CIRCUITS;

EID: 0021389611     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21526     Document Type: Article

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