Architecture for VLSI Design of Reed-Solomon Decoders

IEEE Transactions on Computers

Volumn C-33, Issue 2, 1984, Pages 178-189

  Liu, Kuang Yung ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

BCH decoders; error correcting codes; finite field processors; parallel processing; pipeline processing; Reed Solomon decoders; VLSI

Indexed keywords

CODES, SYMBOLIC - DECODING; COMPUTER SYSTEMS, DIGITAL - PARALLEL PROCESSING;

PIPELINE PROCESSING; REED-SOLOMON DECODERS;

INTEGRATED CIRCUITS, VLSI;

EID: 0021379788     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1984.1676409     Document Type: Article

References (20)

1. R. F. Rice, “Channel coding and data compression system considerations for efficient communication of planetary imaging data,” Tech. Memo. 33–695, Jet Propulsion Laboratory, Pasadena, CA, June 1974.
2. A. Hauptschein, “Practical, high performance concatenated coded spread spectrum channel for JTIDS,” in Proc. Nat. Telecommun. Conf., 1977, p. 35:4-1 to 4–8.
3. K.Y. Liu and J. Lee, “An experimental study of the concatenated Reed-Solomon/Viterbi channel coding system performance and its impact on space communications,” in Proc. Nat. Telecommun. Conf., 1981.
4. K.Y. Liu and K.T. Woo, “The effects of receiver tracking phase error on the performance of the concatenated Reed-Solomon Viterbi channel coding system,” in Proc. Nat. Telecommun. Conf., 1980, pp. 51.5.1-51.5.5.
5. J. P. Odenwalder et al., “Flybrid coding system study,” submitted to NASA Ames Research Center, Linkabit Co., San Diego, CA, Final Rep., Contract NAS-2-6722, Sept. 1972.
6. E. R. Berlekamp, “Technology of error-correcting codes,” Proc. IEEE, vol. 68, May 1980, pp. 567–593.
7. K. Y. Liu, “Architecture for VLSI design of Reed-Solomon encoders,” IEEE Trans. Comput., vol. C-31, pp. 170–175, Feb. 1982.
8. W. W. Peterson and E.J. Weldon, Jr., Error Correcting Codes. Cambridge, MA: MIT Press, 1972.
9. E. R. Berlekamp, “Bit-serial Reed-Solomon encoders,” IEEE Trans. Inform. Theory, vol. IT-28, pp. 869–874, Nov. 1982.
10. —, Algebraic Coding Theory. New York: McGraw-Hill 1968.
11. J. L. Massey, “Shift-register synthesis and BCH decoding,” IEEE Trans. Inform. Theory, vol. IT-15, pp. 122–127, Jan. 1969.
12. W. C. Gore, “Transmitting binary symbols with Reed-Solomon code,” Johns Hopkins Univ., Baltimore, MD, EE Rep. 73–75, Apr. 1973.
13. R. G. Gallager, Information Theory and Reliable Communication. New York: Wiley, 1968.
14. H. T. Kung and C. Leiserson, “Algorithms for VLSI processor arrays,” Introduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley, 1980.
15. J.M. Pollard, “The fast Fourier transform in a finite field,” Math. Comput., vol. 25, pp. 365–374, 1971.
16. A. Michelson, “A fast transform in some Galois fields and an application to decoding Reed-Solomon codes,” in Proc. IEEE Int. Symp. Inform. Theory, 1976, p. 49.
17. R.T. Chien, “Cyclic decoding procedures for Bose-Chaudhuri-Hocquenghem codes,” IEEE Trans. Inform. Theory, vol. IT-10, pp. 357–363, Oct. 1964.
18. D. Mandelbaum, “On decoding of Reed-Solomon codes,” IEEE Trans. Inform. Theory, vol. IT-17, pp. 707–712, 1971.
19. T. C. Bartee and D.I. Schneider, “Computation with finite fields,” Inform. Contr., vol. 6, pp. 79–98, Mar. 1963.
20. B.A. Laws, Jr. and C. K. Rushforth, “A cellular-array multiplier for GF(2m),” IEEE Trans. Comput., vol. C-20, pp. 1573–1578, Dec. 1971.