A Better Understanding of CMOS Latch-Up

IEEE Transactions on Electron Devices

Volumn 31, Issue 1, 1984, Pages 62-67

  Hu, Genda J ^a  

^a PALO ALTO RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS;

EID: 0021204461     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21474     Document Type: Article

References (11)

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3. B. L. Gregory and B. D. Shafer, “Latch-up in CMOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-20, p. 293, Dec. 1973.
4. D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Dep. of Electrical Engineering, Stanford Univ., Tech. Rep. G-201-9, Nov. 1980.
5. G. J. Hu, M. R. Pinto, and S. Kordic, “Two-dimensional simulation of latch-up in CMOS structures,” presented at the 40th Device Research Conf. (Fort Collins, CO), paper VA-5, June 1982.
6. Sze, Physics of Semiconductor Devices. New York: Wiley-Inter-science, 1969.
7. J. F. Gibbons, “A critique of the theory of p-n-p-n devices,” IEEE Trans. Electron Devices, vol. ED-11, p. 406, 1964.
8. W. D. Raburn, “A model for the parasitic SCR in bulk CMOS,” in IEDM Tech. Dig., p. 252, Dec. 1980.
9. A. Ochoa, W. Dawes, and D. Esteich, “Latch-up control in integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-26, p. 5065, 1979.
10. A. Ochoa and P. V. Dressendorfer, “A discussion of the role of distributed effects in latch-up,” IEEE Trans. Nucl. Sci., vol. NS-28, p. 4292, 1981.
11. E. M. Butula, P. E. Cottrell, B. E. Grossman, and K A. Salsburg, IBM J. Res. Develop., vol. 25, p. 218, 1981.