Latchup Model for the Parasitic p-n-p-n Path in Bulk CMOS

IEEE Transactions on Electron Devices

Volumn 31, Issue 1, 1984, Pages 113-120

  Fang, Robert Ching Yuh ^a   Moll, John L ^b  

^a Data General Corporation   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LATCHUP MODEL;

SEMICONDUCTOR DEVICES, MOS;

EID: 0021201527     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21484     Document Type: Article

References (15)

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