MERGED CMOS/BIPOLAR VLSI PROCESS.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1983, Pages 59-62

  Walczyk, Fred ^a   Rubinstein, Jorge ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BURIED LAYER EPITAXIAL PROCESSING; EFFECTIVE BIPOLAR PERFORMANCE; LATCH-UP SUPPRESSION; TAILORED BASE ION IMPLANT; USE OF CMOS TRANSISTORS; USE OF FULLY ISOLATED BIPOLAR TRANSISTORS;

INTEGRATED CIRCUITS, VLSI;

EID: 0020944545     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)