1. 0um N-WELL CMOS/BIPOLAR TECHNOLOGY FOR VLSI CIRCUITS.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1983, Pages 63-66

  Miyamoto, J ^a   Saitoh, S ^a   Momose, H ^a   Shibata, H ^a   Kanzaki, K ^a   Kohyama, S ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

1 MICROMETER CMOS GATES; CMOS/BIPOLAR PROCESS SEQUENCE; FABRICATION PROCESS AND DEVICE STRUCTURE; INPUT/OUTPUT BUFFERS; VLSI ANALOG-DIGITAL COMBINED VLSI SYSTEMS;

INTEGRATED CIRCUITS, VLSI;

EID: 0020943244     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)