OPTIMIZATION OF SUB-MICRON P-CHANNEL FET STRUCTURE.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1983, Pages 534-537

  Chiang, Shang yi ^a   Cham, Kit M ^a   Rung, R D ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ADJUSTMENT OF THRESHOLD VOLTAGE OF TRANSISTOR; DEVICE CHARACTERISTICS; EFFECT OF COUNTER-DOPING CHANNEL IMPLANT JUNCTION DEPTH AND SOURCE/DRAIN JUNCTION DEPTH; P-CHANNEL DEVICE GENERATION BY GEMINI PROGRAM; P-CHANNEL TRANSISTOR FABRICATION;

TRANSISTORS, FIELD EFFECT;

EID: 0020938233     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)