A Class of Redundant Path Multistage Interconnection Networks

IEEE Transactions on Computers

Volumn C-32, Issue 12, 1983, Pages 1099-1108

  Padmanabhan, Krishnan ^a   Lawrie, Duncan H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Array processors; fault tolerance; interconnection networks; multiprocessor systems; nonblocking networks; Omega networks; parallel processing; redundant path networks

Indexed keywords

COMPUTER SYSTEMS, DIGITAL;

EID: 0020895733     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1983.1676170     Document Type: Article

References (14)

1. G. B. Adams and H. J. Siegel, “The extra stage cube: A fault-tolerant interconnection network for supersystems,” IEEE Trans. Comput., vol. C-31, pp. 443-454, May 1982.
2. M. D. Beaudry, “Performance related reliability measures for computing systems,” IEEE Trans. Comput., vol. C-27, pp. 540-547, June 1978.
3. V. E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic. New York: Academic, 1965.
4. Final Report–Numerical Aerodynamic Simulation Feasibility Study, prepared by Burroughs Corporation for Ames Research Center, National Aeronautics and Space Administration, Mar. 1979.
5. K. M. Falavarjani and D. K. Pradhan, “A design of fault-tolerant interconnection networks,” unpublished memo., 1981.
6. T. Y. Feng, “Data manipulating functions in parallel processors and their implementations,” IEEE Trans. Comput., vol. C-23, pp. 309-318, Mar. 1974.
7. L. R. Goke and G. J. Lipovski, “Banyan networks for partitioning multiprocessor systems,” in Proc. 1st Annu. Symp. Comput. Arch., 1974, pp. 21-28.
8. D. H. Lawrie, “Memory-processor connection networks,” Univ. Illinois, Urbana-Champaign, Dep. Comput. Sci. Rep. UIUCDCS-R-73-557, Feb. 1973.
9. C. Leung and J. Dennis, “Design of a fault-tolerant packet communication architecture,” M.I.T. Lab. Comput. Sci. Computat. Structures, Group Memo. 196, July 1980.
10. K. N. Levitt, M. W. Green, and J. Goldberg, “A study of the data commutation problems in a self-repairable multiprocessor,” in Proc. 1968 Spring Joint Comput. Conf., pp. 515-527.
11. J. E. Lilienkamp, D. H. Lawrie, and P.-C. Yew, “A fault tolerant interconnection network using error correcting codes,” Univ. Illinois, Urbana-Champaign, Dep. Comput. Sci. Rep. UIUCDCS-R-82-1094, June 1982.
12. K. Padmanabhan, “Fault-tolerance and performance improvement in shuffle-exchange type networks,” Ph.D. dissertation, Univ. Illinois, Urbana-Champaign, in preparation, 1983.
13. D. S. Parker and C. S. Raghavendra, “The Gamma network: A multiprocessor interconnection network with redundant paths,” in Proc. 9th Annu. Symp. Comput. Arch., 1982, pp. 73-80.
14. C.-L. Wu and T.-Y. Feng, “On a class of multistage interconnection networks,” IEEE Trans. Comput., vol. C-29, pp. 694-702, Aug. 1980.