The Performance of Multistage Interconnection Networks for Multiprocessors

IEEE Transactions on Computers

Volumn C-32, Issue 12, 1983, Pages 1091-1098

  Kruskal, Clyde P ^a   Snir, Marc ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b NEW YORK UNIVERSITY   (United States)

Author keywords

Bandwidth; banyan network; bidelta network; buffered network; circuit switching network; crossbar network; delta network; dilated network; multistage interconnection network; packet switching network; performance analysis; replicated network; simulation; square network; throughput; unbuffered network; uniform network

Indexed keywords

COMPUTER SYSTEMS, DIGITAL;

EID: 0020894692     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1983.1676169     Document Type: Article

References (13)

1. S. Cheemalavagu and M. Malek, “Analysis and simulation of banyan interconnection networks with 2 × 2, 4 × 4, and 8×8 switching elements,” in Proc. Real-Time Syst. Symp., Dec. 1982, pp. 83-89.
2. P.-Y. Chen, “Multiprocessor systems: interconnection networks, memory hierarchy, modeling, and simulations,” Ph.D. dissertation, Univ. Illinois, Urbana, IL, Jan. 1982.
3. D. M. Dias and J. R. Jump, “Packet switching interconnection networks for modular systems,” Computer, vol. 14, pp. 43-54. Dec. 1981.
4. G. R. Goke and G. J. Lipovski, “Banyan networks for partitioning multiprocessor systems,” in Proc. 1st Annu. Symp. Comput. Arch., 1973, pp. 21-28.
5. A. Gottlieb, R. Grishman, C. P. Kruskal, K. P. McAuliffe. L. Rudolph, and M. Snir, “The NYU Ultracomputer-Designing an MIMD, shared-memory parallel machine,” IEEE Trans. Comput., vol. C-32, pp. 175-189, 1983.
6. L. Kleinrock, Queueing Systems, Vol 1: Theory. New York: Wiley, 1975.
7. C. P. Kruskal and M. Snir, “The structure of multistage interconnection networks for multiprocessors,” manuscript; see also, “Some results on multistage interconnection networks for multiprocessors,” NYU Ultracomputer Note 41, in Proc. 1982 Conf. Informat. Sci., Syst., Princeton Univ., Princeton, NJ, Mar. 1982.
8. D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput., vol. C-24, pp. 1145-1155, 1975.
9. J. A. Patel, “Processor-memory interconnections for multiprocessors,” in Proc. 6th Annu. Symp. Comput. Arch., pp. 168-177, Apr. 1979.
10. J. A. Patel, “Performance of processor-memory interconnections for multiprocessors,” IEEE Trans. Comput., vol. C-30, pp. 771-780, 1981.
11. M. C. Pease, “The indirect binary n-cubc microprocessor array,” IEEE Trans. Comput., vol. C-26, pp. 458-473, 1977.
12. J. T. Schwartz, “The Burroughs FMP machine,” Ultracomputer Note 5, Courant Institute, NYU, New York, NY, 1980.
13. M. Snir and J. Solworth, “The Ultraswitch–A VLSI network node for parallel processing,” Ultracomputer Note 39, Courant Institute, NYU, New York, NY, 1982.