SIMPLIFIED BOX (BURIED-OXIDE) ISOLATION TECHNOLOGY FOR MEGABIT DYNAMIC MEMORIES.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1983, Pages 27-30

  Shibata, T ^a   Nakayama, R ^a   Kurosawa, K ^a   Onga, S ^a   Konaka, M ^a   Iizuka, H ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ADDITION TO PROCESS OF NON-CRITICAL MASKING STEP; MOSFET'S FABRICATED ON BOX STRUCTURES; OBSERVED BODY EFFECT IN NARROW CHANNEL DEVICES; TAPER ETCHING;

INTEGRATED CIRCUITS;

EID: 0020884892     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)