DC Holding and Dynamic Triggering Characteristics of Bulk CMOS Latchup

IEEE Transactions on Electron Devices

Volumn 30, Issue 12, 1983, Pages 1647-1655

  Rung, Robert D ^a   Momose, Hiroshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BASE REGION LATERAL CURRENTS; COMPLEMENTARY MOS (CMOS); DC LATCHUP HOLDING AND TRIGGERING CHARACTERISTICS; MINIMUM TURN-ON TIMES; THRESHOLD CURRENT LEVELS;

SEMICONDUCTOR DEVICES, MOS;

EID: 0020873993     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1983.21426     Document Type: Article

References (13)

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2. D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Stanford Electronics Labs Rep. G-201-9, 1980.
3. W. D. Raburn, “A model for the parasitic SCR in bulk CMOS,” in IEDM Tech. Dig., p. 252, 1980.
4. A. Ochoa, W. Dawes, and D. Estreich, “Latchup control in CMOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-26, p. 5065, 1979.
5. P. V. Dressendorfer and A. Ochoa, Jr., “An analysis of the modes of operation of parasitic SCR's,” IEEE Trans. Nucl. Sci., vol. NS-28, p. 4288, 1981.
6. A. Ochoa, Jr., and P. V. Dressendorfer, “A discussion of the role of distributed effects in latchup,” IEEE Trans. Nucl. Sci., vol. NS-28, p. 4292, 1981.
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8. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
9. W. R. Dawes, Jr., and G. F. Derbenwick, “Prevention of CMOS latchup by gold doping,” IEEE Trans. Nucl. Sci., vol. NS-23, p. 2027, 1976.
10. J. R. Adams and R. J. Sokel, “Neutron irradiation for prevention of latchup in MOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-26, p. 5069, 1979.
11. J. E. Schroeder, A. Ochoa, Jr., and P. V. Dressendorfer, “Latchup elimination in bulk CMOS LSI circuits,” IEEE Trans. Nucl. Sci., vol. NS-27, p. 1735, 1980.
12. R. S. Payne, W. N. Grant, and W. J. Bertram, “Elimination of latch-up in bulk CMOS,” in IEDM Tech. Dig., p. 248, 1980.
13. D. B. Estreich, A. Ochoa, Jr., and R. W. Dutton, “An analysis of latch-up prevention in CMOS IC's using an epitaxial buried layer process,” in IEDM Tech. Dig., p. 230, 1978.