Redundancy and Don't Cares in Logic Synthesis

IEEE Transactions on Computers

Volumn C-32, Issue 10, 1983, Pages 947-952

  Brand, Daniel ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Don't cares; logic synthesis; optimization; redundancy; testability

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS;

LOGIC CIRCUITS;

EID: 0020832565     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1983.1676139     Document Type: Article

References (6)

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2. E. J. McCluskey, Jr., “Minimization of Boolean functions,” Bell Syst. Tech. J., vol. 35, pp. 1417-1444, 1956.
3. J. P. Roth, Computer Logic, Testing, and Verification. Potomac, MD: Comput. Sci. Press, 1980.
4. J. A. Darringer, W. H. Joyner, Jr., C. L. Berman, and L. Trevillyan, “Logic synthesis through local transformations,” IBM J. Res. Develop., vol. 25, pp. 272-280, July 1981.
5. R. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testability,” in Proc. 14th Design Automat. Conf, June 1977, pp. 462-468.
6. H. Y. Chang, E. G. Manning, and G. A. Metze, Fault Diagnosis of Digital Systems. New York: Wiley, 1970.