A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM

IEEE Journal of Solid-State Circuits

Volumn 18, Issue 5, 1983, Pages 479-485

  Yoshimoto, Masahiko ^a   Anami, Kenji ^a   Shinohara, Hirofumi ^a   Yoshihara, Tsutomu ^a   Takagi, Hiroshi ^a   Nagao, Shigeo ^a   Rayano, Shinpei ^a   Nakano, Takao ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS RAM; STATIC RAM;

DATA STORAGE, DIGITAL;

EID: 0020830611     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1983.1051981     Document Type: Article

References (7)

1. K. Ochii, K. Hashimoto, H. Yasuda, M. Masuda, H. Nozaw a, and S. Kohyama, “A 15nW standby power 64Kb CMOS RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 260-261.
2. O. Minato, T. Masuhara, T. Sakaki, Y. Sakai, and T. Hayasida, “A HI-CMOSII 8K × 8b static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 256-257.
3. S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, and S. Kohyama, “A 64Kb CMOS RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 258-259.
4. K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, H. Harada, and T. Nakano, “A 35 ns 16K NMOS static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 250-251.
5. S. D. Kang, J. D. Allan, B. Ashmore, T. Herndon, S. Wolpert, and W. C. Brukke, “A 30 ns 16K × 1 fully static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1981, pp. 18-19.
6. A. V. Ebel, G. E. Atwood, E. Y. So, S. S. Liu, V. N. Kynett, R. M. Jecmen, J. Mingo, and H. Dun, “An NMOS 64K static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 254-255.
7. M. Yoshimoto, K. Anami, H. Shinohara, Y. Hirata, T. Yoshihara, and T. Nakano, “Soft error analysis of fully static MOS RAM,” Japan. J. Appl. Phys., vol. 22, suppl. 22-1, pp. 69-73, 1983.