Modeling Thermal Effects on MOS I-V Characteristics

IEEE Electron Device Letters

Volumn 4, Issue 10, 1983, Pages 362-364

  Sharma, D K ^a   Ramanathan, K V ^a  

^a TATA INSTITUTE OF FUNDAMENTAL RESEARCH   (India)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS;

EID: 0020829017     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1983.25764     Document Type: Article

References (5)

1. D. Sharma, J. Gautier, and G. Merckel, “A high voltage SOS MOS circuit,” presented at ESSCIRC 77, Univer. Ulm, Sept. 20–22, 1977.
2. D. Sharma, J. Gautier, and G. Merckel, “Negative dynamic resistance in MOS devices,” IEEE J. Solid State Circuits, vol. SC-13, pp. 378–380, June 1978.
3. M. D. Pocha and R. W. Dutton, “A CAD model for high voltage DMOS transistors,” IEEE J. Solid State Circuits, vol. SC-11, pp. 718–726, Oct. 1976.
4. P. M. Morse and H. Feshbach, Methods of Theoretical Physics. New York: McGraw Hill, 1953.
5. G. Merckel, NATO course, Universite Catholique de Louvain, Belgium, July 19–29, 1977.