Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Films on SiO2

IEEE Electron Device Letters

Volumn 4, Issue 8, 1983, Pages 269-271

  Tsaur, B Y ^a   Silversmith, D J ^a   Fan, J C C ^a   Mountain, R W ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOSFET;

TRANSISTORS, BIPOLAR;

EID: 0020795637     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1983.25729     Document Type: Article

References (14)

1. B-Y. Tsaur, J. C. C. Fan, M. W. Geis, D. J. Silversmith, and R. W Mountain, “Effects of subgrain boundaries on carrier transport in zone-melting-recrystallized Si films on SiO2-coated Si substrates,” IEEE Electron Device Lett., vol. EDL-3, p. 79, 1982.
2. B-Y. Tsaur, J. C. C. Fan, R. L. Chapman, M. W. Geis, D. J. Silversmith, and R. W. Mountain, “SOI/CMOS circuits fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates,” IEEE Electron Device Lett., vol. EDL-3, p. 398, 1982.
3. M. W. Geis, H. I. Smith, B-Y. Tsaur, J. C. C. Fan, D. J. Silversmith, and R. W. Mountain, “Zone-melting recrystallization of Si films with a moveable-strip-heater oven,” J. Electrochem. Soc., vol. 129, p. 2812, 1982.
4. B-Y. Tsaur, J. C. C. Fan, and M. W. Geis, “Microsecond carrier lifetimes in Si films prepared on SiO2-coated Si substrates by zone-melting recrystallization and subsequent epitaxial growth,” Appl. Phys. Lett., vol. 41, p. 83, 1982.
5. G. Zimmer, B. Hoefflinger, and J. Schneider, “A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital system,” IEEE Trans. Electron Devices., vol. ED-26, p. 390, 1979.
6. R. Zuleeg and P. Knoll, “Thin-film lateral bipolar transistor in silicon-on-sapphire structure,” Electron Lett., vol. 3, p. 137, 1967;
7. also A. C. Ipri and J. C. Sarace, “Simultaneous fabrication of CMOS transistors and bipolar devices,” U.S. Patent 4,050, 965.
8. S. N. Lee, R. A. Kjar, and G. Kinoshita, “Island-edge effects in C-MOS/SOS transistors,” IEEE Trans. Electron Devices, vol. ED-25, p. 971, 1978.
9. M. Akiya and T. Kimura, “Substrate bias effect for C-MOS operational amplifier using SIMOX technology,” Electron Lett., vol. 19, p. 36, 1983.
10. See, for example, S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, “Elimination of hot electron gate current by the lightly doped drain-source structure,” in IEDM Tech. Dig., p. 651, 1981.
11. H. C. Lin, T. B. Tan, G. Y. Chang, B. Van der Leest, and N. Formigoni, “Lateral complementary transistor structure for the simultaneous fabrication of functional block,” Proc. IEEE, vol. 52, p. 1491, 1964.
12. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967, ch. 7.
13. K. K. Ng, G. K. Celler, E. I. Povilonis, R. C. Frye, H. J. Leamy, and S. M. Sze, “Effects of grain boundaries on laser crystallized poly-Si MOSFETs,” IEEE Electron Device Lett., vol. EDL-2, p. 316, 1981.
14. J. C. C. Fan, M. W. Geis, and B-Y. Tsaur, “Lateral epitaxy by seeded solidification for growth of single-crystal Si films on insulators,” Appl. Phys. Lett., vol. 38, p. 365, 1981.