Resistance Extraction from Mask Layout Data

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 2, Issue 3, 1983, Pages 145-150

  Horowitz, Mark ^a   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

EID: 0020779529     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1983.1270032     Document Type: Article

References (4)

1. L. Scheffer and R. Apte, “LSI design verification using topology extraction,” in Asilomar Conf. Circuits Systems, and Computers, p. 149, 1978.
2. S. Ramo, J. Whinnery, and T. Van Duzer, Fields and Waves in Communication Electronics. New York: Wiley, 1965, ch. 3.
3. T. Ozaki, J. Yoshida, and M. Kosaka, “PANAMAP-1: A mask pattern analysis program for IC/LSI,” in Proc. Int. Symp. Circuits and Systems, pp. 1020-1026, 1980.
4. H. Yoshimura, K. Tansho, N. Ohwada, and T. Nishide, “An algorithm for resistance calculation from IC mask pattern information,” in Proc. Int. Symp. Circuits and Systems, pp. 478-481, 1979.