The Modeling of Resistive Interconnects for Integrated Circuits

IEEE Journal of Solid-State Circuits

Volumn 18, Issue 2, 1983, Pages 200-203

  Antinone, Robert J ^a   Brown, Gerald W ^b  

^a Safety and Mission Assurance Manager Space Systems Loral   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

EID: 0020737036     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1983.1051922     Document Type: Article

References (6)

1. M. I. Elmasry, “Interconnect delays in MOSFET VLSI,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 585-591, Oct. 1981.
2. B. L. Crowder and S. Zirinsky, “1 µm MOSFET VLSI technology: Part VII-Metal silicide interconnection technology-A future perspective,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 291-293, Apr. 1979.
3. S. K. Ghandi, Theory and Practice of Microelectronics. New York: Wiley, 1968.
4. C. S. Meyer, D. K. Lynn, and D. J. Hamilton, Eds., Analysis and Design of Integrated Circuits. New York: McGraw-Hill, 1968.
5. L. N. Dworsky, Modern Transmission Line Theory and Applications. New York: Wiley, 1979.
6. A. E. Ruehli and P. A. Brennan, “Accurate metallization capacitances for integrated circuits and packages,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 289-290, Aug. 1973.