Hierarchical channel router

Integration, the VLSI Journal

Volumn 1, Issue 1, 1983, Pages 21-38

  Burstein, Michael ^a   Pelavin, Richard ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF ROCHESTER   (United States)

Author keywords

Channel router; hierarchy; N * n log m time

Indexed keywords

ELECTRIC WIRING;

PRINTED CIRCUITS;

EID: 0020736321     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9260(83)90004-4     Document Type: Article

References (12)

1. Circuit layout
2. A dogleg channel router
3. LTX - A minicomputer-based system for automatic LSI layout
4. Wire routing by optimizing channel assignment
5. Efficient algorithms for channel routing
6. A ‘greedy’ channel router
7. Provably good channel routing algorithms
8. Algorithms for integrated circuit layout: An analytic approach
9. An optimum channel-routing algorithm for polycell layouts of integrated circuits
10. Rectilinear Steiner trees: Efficient special case algorithms
11. Hierarchical channel router