Self-Calibration Technique for A/D Converters

IEEE Transactions on Circuits and Systems

Volumn 30, Issue 3, 1983, Pages 188-190

  Lee, Hae Seung ^a   Hodges, David A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, DIGITAL; LOGIC DEVICES - GATES;

DIGITAL ALGORITHMS; LINEARITY ERRORS; SELF CALIBRATION TECHNIQUES;

DATA CONVERSION, ANALOG TO DIGITAL;

EID: 0020720035     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1983.1085339     Document Type: Article

References (6)

1. Z. G. Boyacigiller, B. Weir, and P. D. Bradshaw, “An error-correcting 14b/20 µs CMOS A/D converter,” 1981 IEEE Int. Solid-State Circuits Conf. Dig. of Technical Papers, vol. XXIV, pp. 62-63.
2. K. Maio, M. Hotta, N. Yokozawa, M. Nagata, K. Kaneko, and T. Iwasaki, “An Untrimmed D/A Converter with 14-bit Resolution,” IEEE Trans. Solid-State Circuits, vol. SC-16, Dec. 1981.
3. J. Domogalla (Texas Instruments), “Algorithmic error correction for MOS charge redistribution based analog to digital converter,” unpublished.
4. J. L. McCreary and P. R. Gray, “All MOS charge redistribution analog-to-digital conversion techniques–Part I,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975.
5. J. L. McCreary and D. A. Sealer, “Precision capacitor ratio measurement technique for integrated circuit capacitor arrays,” IEEE Trans. Instrum. Meas., vol. IM-28, Mar. 1979.
6. A. R. Hamade, “A single chip all-MOS 8-bit A/D converter,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 785-791, Dec. 1978.