Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing

IEEE Transactions on Computers

Volumn C-32, Issue 2, 1983, Pages 190-194

  Barzilai, Zeev ^a   Coppersmith, Don ^a   Rosenberg, Arnold L ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b DUKE UNIVERSITY   (United States)

Author keywords

Linear feedback shift registers (LFSR); primitive polynomials; VLSI self testing

Indexed keywords

INTEGRATED CIRCUITS, VLSI;

COMPUTERS, DIGITAL;

EID: 0020708314     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1983.1676202     Document Type: Article

References (7)

1. Z. Barzilai, J. Savir, G. Markowsky, and M. G. Smith, “The weighted syndrome sums approach to VLSI testing,” IBM Research Rep. RC-8475, Dec. 1980; also in IEEE Trans. Comput., vol. C-30, Dec. 1981.
2. E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testability,” in Proc. 14th Design Automation Conf. June 1977.
3. F. J. Hill and G. R. Peterson, Digital Systems: Hardware Organization and Design, 2nd ed. New York: Wiley, 1978.
4. B. Konemann, J. Mucha, and G. Zwiehoff, “Built-in test for complex digital integrated circuits,” IEEE J. Solid-State Circuits, vol SC-15, June 1980.
5. W. W. Peterson, Error Correcting Codes. Cambridge, MA: M.I.T. Press, 1961.
6. A. Lempel and M. Cohn, “Design of universal test sequences for VLSI,” Sperry Research Center, Jan. 1982, submitted for publication.
7. D. Tang, personal communication.