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Volumn , Issue , 1983, Pages 411-418
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TIMING ANALYSIS FOR nMOS VLSI.
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NONE
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Author keywords
[No Author keywords available]
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Indexed keywords
BIPOLAR VS. MOS TECHNOLOGY;
DETERMINING TRANSISTOR USAGE;
FINDING CRITICAL PATHS;
IMPROVING DESIGN PERFORMANCE;
NMOS CIRCUITRY;
STATIC CHECKING;
INTEGRATED CIRCUITS, VLSI;
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EID: 0020552322
PISSN: 01467123
EISSN: None
Source Type: None
DOI: 10.1109/dac.1983.1585685 Document Type: Conference Paper |
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Times cited : (42)
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References (0)
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