Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs

Electronics Letters

Volumn 18, Issue 3, 1982, Pages 119-121

  Yamasaki, K ^a   Asai, K ^a   Mizutani, T ^a   Kurumada, K ^a  

^a Musashino Electrical Communication Lab   (Japan)

Author keywords

Integrated circuits; Semiconductor devices and materials

Indexed keywords

SEMICONDUCTING GALLIUM ARSENIDE - ION IMPLANTATION;

INTEGRATED CIRCUITS;

EID: 0020474506     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19820080     Document Type: Article

References (4)

1. ASAI, K., INO, M., KURUMADA, K., KAWASAKI, Y., and OHMORI, M.: ‘GaAs E/D FET technology for applications to static RAM’. Proceedings of symposium on gallium arsenide and related compounds, Oiso, Japan, 1981
2. SPICER, W. E., CHYE, P. W., SKEATH, P. R., SU, C. Y., and LINDAU, I.: ‘New and unified model for Schottky barrier and III-V insulator interface states formation’, J. Vac. Sci. & Technol, 1979, 16, pp. 1422-1433
3. YAMASAKI, K., ASAI, K., and KURUMADA, K. : ‘Reactive ion beam etching—application to GaAs integrated circuit fabrication’. Proceedings of symposium on dry processes, Tokyo, 1981, pp. 105-112
4. YOKOYAMA, N., MIMURA, T., FUKUTA, M., and ISHIKAWA, M.: ‘A self-aligned source/drain planar device for ultrahigh-speed GaAs MESFET VLSIs’. IEEE international solid-state circuits conference, Digest of technical papers, New York, 1981, pp. 218-219