CHARACTERIZATION OF CMOS LATCH-UP.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1982, Pages 454-457

  Huang, C C ^a   Hartranft, M D ^a   Pu, N F ^a   Yue, C ^a   Rahn C , ^a   Schrankler, J ^a   Kirchner, G D ^a   Hampton, F L ^a   Hendrickson, T E ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFERS; INPUT PROTECTION; INVERTERS; LATCH-UP; N-WELL CMOS PROCESS; PARASITIC SCR;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0020247835     PISSN: 01631918     EISSN: None     Source Type: None    
DOI: 10.1109/iedm.1982.190323     Document Type: Conference Paper

References (0)